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TD62008AFWG Fiches technique(PDF) 3 Page - Toshiba Semiconductor |
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TD62008AFWG Fiches technique(HTML) 3 Page - Toshiba Semiconductor |
3 / 8 page TD62008AFWG 2007-10-16 3 Test Circuit 1. ICEX 2. VCE (sat) 3. hFE IN C FE I I h = 4. IIN (ON), IIN (OFF) 5. IR 6. VF 7. tON, tOFF Note 1: Pulse width 50 μs Duty cycle 10% Output impedance 50 Ω tr ≤ 5 ns, tf ≤ 10 ns Note 2: CL includes probe and jig capacitance Precautions for Use This IC does not include built-in protection circuits for excess current or overvoltage. If this IC is subjected to excess current or overvoltage, it may be destroyed. Hence, the utmost care must be taken when systems which incorporate this IC are designed. Utmost care is necessary in the design of the output line, COMMON and GND line since the IC may be destroyed due to short-circuit between outputs, air contamination fault, or fault by improper grounding. Input Pulse Generator Open VOUT RL CL = 15 pF (Note 2) Output (Note 1) Input Output tr 90% 50% 10% tON 50% 50% 50% 10% 90% tf tOFF VOL VOH 0 VIH 50 μs IR Open VR Open Open VIN Open IIN (ON) IIN (OFF) Open ICEX VIN VCE Open IOUT VIN VCE (sat) IF Open Open VF Open IC VCE IIN |
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