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TC74LCX374F Fiches technique(PDF) 4 Page - Toshiba Semiconductor

No de pièce TC74LCX374F
Description  Low-Voltage Octal D-Type Flip-Flop with 5-V Tolerant Inputs and Outputs
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Fabricant  TOSHIBA [Toshiba Semiconductor]
Site Internet  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TC74LCX374F Fiches technique(HTML) 4 Page - Toshiba Semiconductor

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TC74LCX374F/FT/FK
2007-10-19
4
Electrical Characteristics
DC Characteristics (Ta = −40 to 85°C)
Characteristics
Symbol
Test Condition
VCC (V)
Min
Max
Unit
H-level
VIH
2.7 to 3.6
2.0
Input voltage
L-level
VIL
2.7 to 3.6
0.8
V
IOH = −100 μA
2.7 to 3.6
VCC
0.2
IOH = −12 mA
2.7
2.2
IOH = −18 mA
3.0
2.4
H-level
VOH
VIN = VIH or VIL
IOH = −24 mA
3.0
2.2
IOL = 100 μA
2.7 to 3.6
0.2
IOL = 12 mA
2.7
0.4
IOL = 16 mA
3.0
0.4
Output voltage
L-level
VOL
VIN = VIH or VIL
IOL = 24 mA
3.0
0.55
V
Input leakage current
IIN
VIN = 0 to 5.5 V
2.7 to 3.6
±5.0
μA
3-state output OFF state current
IOZ
VIN = VIH or VIL
VOUT = 0 to 5.5 V
2.7 to 3.6
±5.0
μA
Power-off leakage current
IOFF
VIN/VOUT = 5.5 V
0
10.0
μA
VIN = VCC or GND
2.7 to 3.6
10.0
Quiescent supply current
ICC
VIN/VOUT = 3.6 to 5.5 V
2.7 to 3.6
±10.0
Increase in ICC per input
ΔICC
VIH = VCC 0.6 V
2.7 to 3.6
500
μA
AC Characteristics (Ta = −40 to 85°C)
Characteristics
Symbol
Test Condition
VCC (V)
Min
Max
Unit
2.7
Maximum clock frequency
fmax
Figure 1, Figure 2
3.3
± 0.3
150
MHz
2.7
9.5
Propagation delay time
(CK-Q)
tpLH
tpHL
Figure 1, Figure 2
3.3
± 0.3
1.5
8.5
ns
2.7
9.5
Output enable time
tpZL
tpZH
Figure 1, Figure 3
3.3
± 0.3
1.5
8.5
ns
2.7
8.5
Output disable time
tpLZ
tpHZ
Figure 1, Figure 3
3.3
± 0.3
1.5
7.5
ns
2.7
4.0
Minimum pulse width
(CK)
tw (H)
tw (L)
Figure 1, Figure 2
3.3
± 0.3
3.3
ns
2.7
2.5
Minimum setup time
ts
Figure 1, Figure 2
3.3
± 0.3
2.5
ns
2.7
1.5
Minimum hold time
th
Figure 1, Figure 2
3.3
± 0.3
1.5
ns
2.7
Output to output skew
tosLH
tosHL
(Note)
3.3
± 0.3
1.0
ns
Note:
Parameter guaranteed by design.
(tosLH = |tpLHm − tpLHn|, tosHL = |tpHLm − tpHLn|)


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