TC74HC390AP_07 datasheet(1/11 Pages) TOSHIBA

No de pièce	TC74HC390AP

Description	CMOS Digital Integrated Circuit Silicon Monolithic Dual Decade Counter

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Fabricant	TOSHIBA [Toshiba Semiconductor]

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TC74HC390AP/AF/AFN

2007-10-01

1

TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic

TC74HC390AP,TC74HC390AF,TC74HC390AFN

Dual Decade Counter

The TC74HC390A is a high speed CMOS DUAL DECADE

COUNTER fabricated with silicon gate C2MOS technology.

It achieves the high speed operation similar to equivalent

LSTTL while maintaining the CMOS low power dissipation.

It consists of two independent 4-bit counters, each composed of

a divide-by-two and a divide-by-five counter. The divide-by-two

counter is incremented on the negative going transition of clock A

( CKA ). The divided-by-five counter is incremented on the

negative going transition of clock B ( CKB ). The counter can be

cascaded to form decade, bi-quinary, or various combinations up

to a divide-by-100 counter. When the CLR input is set high, the

Q outputs are set to low independent of the clock inputs.

All inputs are equipped with protection circuits against static

discharge or transient excess voltage.

Features

• High speed: fmax = 84 MHz (typ.) at VCC = 5 V

• Low power dissipation: ICC = 4 μA (max) at Ta = 25°C

• High noise immunity: VNIH = VNIL = 28% VCC (min)

• Output drive capability: 10 LSTTL loads

• Symmetrical output impedance: |IOH| = IOL = 4 mA (min)

•

Balanced propagation delays: tpLH ∼− tpHL

• Wide operating voltage range: VCC (opr) = 2~6 V

• Pin and function compatible with 74LS390

Pin Assignment

Note: xxxFN (JEDEC SOP) is not available in

Japan.

TC74HC390AP

TC74HC390AF

TC74HC390AFN

Weight

DIP16-P-300-2.54A

: 1.00 g (typ.)

SOP16-P-300-1.27A

: 0.18 g (typ.)

SOL16-P-150-1.27

: 0.13 g (typ.)

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