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TC74AC373P Fiches technique(PDF) 5 Page - Toshiba Semiconductor

No de pièce TC74AC373P
Description  CMOS Digital Integrated Circuit Silicon Monolithic Octal D-Type Latch with 3-State Output
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Fabricant  TOSHIBA [Toshiba Semiconductor]
Site Internet  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TC74AC373P Fiches technique(HTML) 5 Page - Toshiba Semiconductor

  TC74AC373P_07 Datasheet HTML 1Page - Toshiba Semiconductor TC74AC373P_07 Datasheet HTML 2Page - Toshiba Semiconductor TC74AC373P_07 Datasheet HTML 3Page - Toshiba Semiconductor TC74AC373P_07 Datasheet HTML 4Page - Toshiba Semiconductor TC74AC373P_07 Datasheet HTML 5Page - Toshiba Semiconductor TC74AC373P_07 Datasheet HTML 6Page - Toshiba Semiconductor TC74AC373P_07 Datasheet HTML 7Page - Toshiba Semiconductor TC74AC373P_07 Datasheet HTML 8Page - Toshiba Semiconductor TC74AC373P_07 Datasheet HTML 9Page - Toshiba Semiconductor  
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TC74AC373P/F/FT
2007-10-01
5
AC Characteristics (CL = 50 pF, RL = 500 Ω, input: tr = tf = 3 ns)
Test Condition
Ta = 25°C
Ta =
−40 to 85°C
Characteristics
Symbol
VCC (V)
Min
Typ.
Max
Min
Max
Unit
Propagation delay
time
(LE-Q)
tpLH
tpHL
3.3 ± 0.3
5.0 ± 0.5
7.7
6.1
13.2
8.7
1.0
1.0
15.0
10.0
ns
Propagation delay
time
(D-Q)
tpLH
tpHL
3.3 ± 0.3
5.0 ± 0.5
7.6
5.8
12.9
8.3
1.0
1.0
14.7
9.5
ns
Output enable time
tpZL
tpZH
3.3 ± 0.3
5.0 ± 0.5
7.6
6.1
12.9
8.7
1.0
1.0
14.7
10.0
ns
Output disable time
tpLZ
tpHZ
3.3 ± 0.3
5.0 ± 0.5
7.0
5.4
11.0
7.5
1.0
1.0
12.5
8.5
ns
Input capacitance
CIN
5
10
10
pF
Output capacitance
COUT
10
pF
Power dissipation
capacitance
CPD
(Note)
38
pF
Note:
CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load.
Average operating current can be obtained by the equation:
ICC (opr) = CPD·VCC·fIN·ICC/8 (per latch)
And the total CPD when n pcs. of latch operate can be gained by the following equation:
CPD (total) = 26 + 12·n


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