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TC59LM906AMG-50 Fiches technique(PDF) 11 Page - Toshiba Semiconductor |
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TC59LM906AMG-50 Fiches technique(HTML) 11 Page - Toshiba Semiconductor |
11 / 59 page TC59LM914/06AMG-37,-50 2004-08-20 11/59 Rev 1.0 AC TEST CONDITIONS SYMBOL PARAMETER VALUE UNIT NOTES VIH (min) Input High Voltage (minimum) VREF + 0.2 V VIL (max) Input Low Voltage (maximum) VREF − 0.2 V VREF Input Reference Voltage VDDQ/2 V VTT Termination Voltage VREF V VSWING Input Signal Peak to Peak Swing 0.7 V Vr Differential Clock Input Reference Level VX (AC) V VID (AC) Input Differential Voltage 1.0 V SLEW Input Signal Minimum Slew Rate 2.5 V/ns VOTR Output Timing Measurement Reference Voltage VDDQ/2 V 9 Note: (1) Transition times are measured between VIH min (DC) and VIL max (DC). Transition (rise and fall) of input signals have a fixed slope. (2) If the result of nominal calculation with regard to tCK contains more than one decimal place, the result is rounded up to the nearest decimal place. (i.e., tDQSS = 0.75 × tCK, tCK = 5 ns, 0.75 × 5 ns = 3.75 ns is rounded up to 3.8 ns.) (3) These parameters are measured from the differential clock (CLK and CLK ) AC cross point. (4) These parameters are measured from signal transition point of DQS crossing VREF level. In case of DQS enable mode, these parameters are measured from the crossing point of DQS and DQS . (5) The tREFI (max) applies to equally distributed refresh method. The tREFI (min) applies to both burst refresh method and distributed refresh method. In such case, the average interval of eight consecutive Auto-Refresh commands has to be more than 400 ns always. In other words, the number of Auto-Refresh cycles which can be performed within 3.2 µs (8 × 400 ns) is to 8 times in the maximum. (6) Low Impedance State is specified at VDDQ/2 ± 0.2 V from steady state. (7) High Impedance State is specified where output buffer is no longer driven. (8) These parameters depend on the clock jitter. These parameters are measured at stable clock. (9) Output timing is measured by using Normal driver strength at VDDQ = 1.7V∼1.9V. Output timing is measured by using Strong driver strength at VDDQ = 1.4V∼1.6V. (10) These parameters are measured at tCK = minimum∼6.0ns. When tCK is longer than 6.0ns, these parameters are specified as below for all Speed version tCKQS (MIN/MAX) = −0.6ns / 0.6ns, tAC (MIN/MAX) = −0.65ns / 0.65ns SLEW = (VIH min (AC) − VIL max (AC))/∆T VIH min (AC) ∆T VREF VIL max (AC) VSWING ∆T VSS VDDQ AC Test Load Measurement point Output VTT 25 Ω |
Numéro de pièce similaire - TC59LM906AMG-50 |
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Description similaire - TC59LM906AMG-50 |
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