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CXK79M36C165GB Fiches technique(PDF) 4 Page - Sony Corporation

No de pièce CXK79M36C165GB
Description  18Mb 1x1Dp LVCMOS High Speed Synchronous SRAMs (256Kb x 72 or 512Kb x 36)
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Fabricant  SONY [Sony Corporation]
Site Internet  http://www.sony.co.jp
Logo SONY - Sony Corporation

CXK79M36C165GB Fiches technique(HTML) 4 Page - Sony Corporation

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SONY®
ΣRAM
CXK79M72C165GB / CXK79M36C165GB
Preliminary
18Mb 1x1Dp, LVCMOS, rev 1.3
4 / 29
November 18, 2003
Pin Description
Symbol
Type
Quantity
Description
A
Input
x72 = 16
x36 = 17
Address Inputs - Registered on the rising edge of CK.
A1, A0
Input
2
Address Inputs 1,0 - Registered on the rising edge of CK. Initialize burst counter.
DQa, DQb
DQc, DQd
DQe, DQf
DQg, DQh
I/O
x72 = 72
x36 = 36
Data Inputs / Outputs - Registered on the rising edge of CK during write operations.
Driven from the rising edge of CK during read operations.
DQa - indicates Data Byte a
DQb - indicates Data Byte b
DQc - indicates Data Byte c
DQd - indicates Data Byte d
DQe - indicates Data Byte e
DQf - indicates Data Byte f
DQg - indicates Data Byte g
DQh - indicates Data Byte h
CK
Input
1
Input Clock
CQ1, CQ1
CQ2, CQ2
Output
4
Output Clocks
E1
Input
1
Chip Enable Control Input - Registered on the rising edge of CK.
E1 = 0
enables the device to accept read and write commands.
E1 = 1
disables the device.
See the Clock Truth Table section for further information.
E2, E3
Input
2
Programmable Chip Enable Control Inputs - Registered on the rising edge of CK. See
the Clock Truth Table and Depth Expansion sections for further information.
EP2, EP3
Input
2
Programmable Chip Enable Active-Level Select Inputs - These pins must be tied
“high” or “low” at power-up. See the Clock Truth Table and Depth Expansion sec-
tions for further information.
ADV
Input
1
Address Advance Control Input - Registered on the rising edge of CK.
ADV = 0
loads a new address and begins a new operation when the device is
enabled.
ADV = 1
increments the address and continues the previous operation when the
device is enabled.
See the Clock Truth Table section for further information.
W
Input
1
Write Enable Control Input - Registered on the rising edge of CK.
W = 0
specifies a write operation when ADV = 0 and the device is enabled.
W = 1
specifies a read operation when ADV = 0 and the device is enabled.
See the Clock Truth Table section for further information.
Ba, Bb, Bc
Bd, Be, Bf
Bg, Bh
Input
x72 = 8
x36 = 4
Byte Write Enable Control Inputs - Registered on the rising edge of CK.
Ba = 0
specifies write Data Byte a during a write operation
Bb = 0
specifies write Data Byte b during a write operation
Bc = 0
specifies write Data Byte c during a write operation
Bd = 0
specifies write Data Byte d during a write operation
Be = 0
specifies write Data Byte e during a write operation
Bf = 0
specifies write Data Byte f during a write operation
Bg = 0
specifies write Data Byte g during a write operation
Bh = 0
specifies write Data Byte h during a write operation
See the Clock Truth Table section for further information.
ZQ
Input
1
Output Impedance Control Input - This pin must be tied “high” or “low” at power-up.
ZQ = 0 selects ~25
Ω output impedance
ZQ = 1 selects ~50
Ω output impedance
Note: This pin can also be left unconnected. It is weakly pulled “high” internally.


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