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SM8952AL25 Fiches technique(PDF) 6 Page - SyncMOS Technologies,Inc |
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SM8952AL25 Fiches technique(HTML) 6 Page - SyncMOS Technologies,Inc |
6 / 16 page SyncMOS Technologies International, Inc. SM8951A/8952A 8-Bits Micro-controller With 4/8KB flash embedded Specifications subject to change without notice contact your sales representatives for the most recent information. Ver 2.1 SM8951A/8952A 08/2006 6 Watch Dog Timer Registers - WDT Control Register (WDTC, $9F) WDTE R Clear Unused Unused PS2 PS1 PS0 Read / Write: R/W - - - - R/W R/W R/W Reset value: 0 * 0 * * 0 0 0 MSB LSB WDTE : Watch Dog Timer enable bit CLEAR : Watch Dog Timer reset bit If CLEAR bit set to 1 , Watch Dog Timer will be reset . User don’t reset value to 0 . PS2~PS0:clock source divider bit PS [2:0] Divider (OSC in) Time Period (ms) @40MHZ 000 8 13.1 001 16 26.21 010 32 52.42 011 64 104.8 100 128 209.71 101 256 419.43 110 512 838.86 111 1024 1677.72 Watch Dog Timer Register - System Control Register (SCONF, $BFH) bit-7 bit-0 WDR Unused Unused Unused Unused Unused Unused ALEI Read / Write: R/W - - - - - - R/W Reset value: 0 * * * * * * 0 WDR : Watch Dog Timer Reset. When system reset by Watch Dog Timer overflow, WDR will be set to 1 ALEI : ALE output inhibit bit, to reduce EMI The bit 7(WDR) of SCONF is Watch Dog Timer Reset bit. It will be set to 1 when reset signal generated by WDT overflow. User should check WDR bit whenever un-predicted reset happened. Reduce EMI Function The SM8951A/8952A allows user to reduce the EMI emission by setting 1 to the bit 0 (ALEI) of SCONF register. This function will inhibit the clock signal in Fosc/6Hz output to the ALE pin. This function is available when there is no external pro gram memory or no external data RAM in the system. |
Numéro de pièce similaire - SM8952AL25 |
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Description similaire - SM8952AL25 |
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