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SM34020APCM40 Fiches technique(PDF) 7 Page - Texas Instruments |
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SM34020APCM40 Fiches technique(HTML) 7 Page - Texas Instruments |
7 / 89 page SM34020APCM40 GRAPHICS SYSTEM PROCESSOR SGLS361 − JULY 2006 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions (Continued) TERMINAL DESCRIPTION NAME TYPE † DESCRIPTION Video Interface (continued) HSYNC I/O Horizontal synchronization. HSYNC is the horizontal synchronization signal that controls external video circuitry. HSYNC can be programmed to be either an input or an output by modifying a control bit in the DPYCTL register. As an output, HSYNC is the active-low horizontal-sync signal generated by the SM34020APCM40 on-chip video timers. As an input, HSYNC synchronizes the SM34020APCM40 video-control registers to externally generated horizontal-sync pulses. The actual synchronization can be programmed to begin at any VCLK cycle; this allows for any external pipelining of signals. Immediately following reset, HSYNC is configured as an input. SCLK I Serial data clock. SCLK is the same as the signal that drives VRAM serial data registers. SCLK allows the SM34020APCM40 to track the VRAM serial-data-register count, providing serial-register transfer and midline-reload cycles. (SCLK can be asynchronous to VCLK; however, it typically has a frequency that is a multiple of the VCLK frequency.) VCLK I Video clock. VCLK is derived from a multiple of the video system dot clock and is used internally to drive the video timing logic. VSYNC I/O Vertical synchronization. VSYNC is the vertical synchronization signal that controls external video circuitry. VSYNC can be programmed to be either an input or an output by modifying a control bit in the DPYCTL register. As an output, VSYNC is the active-low vertical-sync signal generated by the SM34020APCM40 on-chip video timers. As an input, VSYNC synchronizes the SM34020APCM40 video-control registers to externally generated vertical-sync pulses. The actual synchronization can be programmed to begin at any horizontal line; this allows for any external pipelining of signals. Immediately following reset, VSYNC is configured as an input. † I = input, O = output |
Numéro de pièce similaire - SM34020APCM40 |
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Description similaire - SM34020APCM40 |
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