 |
Moteur de recherche de fiches techniques de composants électroniques |
|
|
Moteur de recherche de fiches techniques de composants électroniques |
|
SM34020APCM40 Fiches technique(PDF) 7 Page - Texas Instruments |
|
|
||||||||||||||||||||||||||||||
SM34020APCM40 Fiches technique(HTML) 7 Page - Texas Instruments |
|
|
7 / 89 page  SM34020APCM40 GRAPHICS SYSTEM PROCESSOR SGLS361 − JULY 2006 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions (Continued) TERMINAL DESCRIPTION NAME TYPE † DESCRIPTION Video Interface (continued) HSYNC I/O Horizontal synchronization. HSYNC is the horizontal synchronization signal that controls external video circuitry. HSYNC can be programmed to be either an input or an output by modifying a control bit in the DPYCTL register. As an output, HSYNC is the active-low horizontal-sync signal generated by the SM34020APCM40 on-chip video timers. As an input, HSYNC synchronizes the SM34020APCM40 video-control registers to externally generated horizontal-sync pulses. The actual synchronization can be programmed to begin at any VCLK cycle; this allows for any external pipelining of signals. Immediately following reset, HSYNC is configured as an input. SCLK I Serial data clock. SCLK is the same as the signal that drives VRAM serial data registers. SCLK allows the SM34020APCM40 to track the VRAM serial-data-register count, providing serial-register transfer and midline-reload cycles. (SCLK can be asynchronous to VCLK; however, it typically has a frequency that is a multiple of the VCLK frequency.) VCLK I Video clock. VCLK is derived from a multiple of the video system dot clock and is used internally to drive the video timing logic. VSYNC I/O Vertical synchronization. VSYNC is the vertical synchronization signal that controls external video circuitry. VSYNC can be programmed to be either an input or an output by modifying a control bit in the DPYCTL register. As an output, VSYNC is the active-low vertical-sync signal generated by the SM34020APCM40 on-chip video timers. As an input, VSYNC synchronizes the SM34020APCM40 video-control registers to externally generated vertical-sync pulses. The actual synchronization can be programmed to begin at any horizontal line; this allows for any external pipelining of signals. Immediately following reset, VSYNC is configured as an input. † I = input, O = output |
Numéro de pièce similaire - SM34020APCM40 |
|
Description similaire - SM34020APCM40 |
|
|
Lien URL |
| Politique de confidentialité |
| ALLDATASHEET.FR |
| ALLDATASHEET vous a-t-il été utile ? [ DONATE ] |
À propos de Alldatasheet | Publicité | Contactez-nous | Politique de confidentialité | Echange de liens | Fabricants All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
French ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
