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TLC5615CDRG4 Fiches technique(PDF) 11 Page - Texas Instruments

No de pièce TLC5615CDRG4
Description  10-BIT DIGITAL-TO-ANALOG CONVERTERS
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DAC Code
Output
Voltage
0 V
Negative
Offset
POWER-SUPPLY BYPASSING AND GROUND MANAGEMENT
0.1
µF
Analog Ground Plane
1
2
3
4
8
7
6
5
SAVING POWER
TLC5615C, TLC5615I
SLAS142E – OCTOBER 1996 – REVISED JUNE 2007
The output amplifier attempts to drive the output to a negative voltage. However, because the most negative
supply rail is ground, the output cannot drive below ground and clamps the output at 0V.
The output voltage then remains at zero until the input code value produces a sufficient positive output voltage
to overcome the negative offset voltage, resulting in the transfer function shown in Figure 14.
Figure 14. Effect of Negative Offset (Single Supply)
This offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the
dotted line if the output buffer could drive below the ground rail.
For a DAC, linearity is measured between zero-input code (all inputs '0') and full-scale code (all inputs '1') after
offset and full scale are adjusted out or accounted for in some way. However, single supply operation does not
allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity is
measured between full-scale code and the lowest code that produces a positive output voltage. For the
TLC5615, the zero-scale (offset) error is
±3LSB maximum. The code is calculated from the maximum
specification for the negative offset.
Printed circuit boards that use separate analog and digital ground planes offer the best system performance.
Wire-wrap boards do not perform well and should not be used. The two ground planes should be connected
together at the low-impedance power-supply source. The best ground connection may be achieved by
connecting the DAC AGND terminal to the system analog ground plane making sure that analog ground currents
are well managed and there are negligible voltage drops across the ground plane.
A 0.1
µF ceramic-capacitor bypass should be connected between V
DD and AGND and mounted with short leads
as close as possible to the device. Use of ferrite beads may further isolate the system analog supply from the
digital power supply.
Figure 15 shows the ground plane layout and bypassing technique.
Figure 15. Power-Supply Bypassing
Setting the DAC register to all 0s minimizes power consumption by the reference resistor array and the output
load when the system is not using the DAC.
11
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