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TPS51100 Fiches technique(PDF) 8 Page - Texas Instruments |
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TPS51100 Fiches technique(HTML) 8 Page - Texas Instruments |
8 / 20 page TPS51100 SLUS600B − APRIL 2004 − REVISED NOVEMBER 2005 8 www.ti.com DETAILED DESCRIPTION W PKG + T J(max) * TA(max) q JA where D TJ(max) is 125°C D TA(max) is the maximum ambient temperature in the system D θJA is the thermal resistance from the silicon junction to the ambient This thermal resistance strongly depends on the board layout. TPS51100 is assembled in a thermally enhanced PowerPAD package that has exposed die pad underneath the body. For improved thermal performance, this die pad needs to be attached to ground trace via thermal land on the PCB. This ground trace acts as a heat sink/spread. The typical thermal resistance, 57.7 °C/W, is achieved based on a 3 mm × 2 mm thermal land with 2 vias without air flow. It can be improved by using larger thermal land and/or increasing vias number. For example, assuming 3 mm × 3 mm thermal land with 4 vias without air flow, it is 45.4°C/W. Further information about PowerPAD and its recommended board layout is described in the application note (SLMA002). This document is available at www.ti.com. LAYOUT CONSIDERATIONS Consider the following points before the layout of TPS51100 design begins. D The input bypass capacitor for VLDOIN should be placed to the pin as close as possible with short and wide connection. D The output capacitor for VTT should be placed close to the pin with short and wide connection in order to avoid additional ESR and/or ESL of the trace. D VTTSNS should be connected to the positive node of VTT output capacitor(s) as a separate trace from the high current power line and is strongly recommended to avoid additional ESR and/or ESL. If it is needed to sense the voltage of the point of the load, it is recommended to attach the output capacitor(s) at that point. Also, it is recommended to minimize any additional ESR and/or ESL of ground trace between GND pin and the output capacitor(s). D Consider adding LPF at VTTSNS in case ESR of the VTT output capacitor(s) is larger than 2 mΩ. D VDDQSNS can be connected separately from VLDOIN. Remember that this sensing potential is the reference voltage of VTTREF. Avoid any noise generative lines. D Negative node of VTT output capacitor(s) and VTTREF capacitor should be tied together by avoiding common impedance to the high current path of the VTT source/sink current. D GND (Signal GND) pin node represents the reference potential for VTTREF and VTT outputs. Connect GND to negative nodes of VTT capacitor(s), VTTREF capacitor and VDDQ capacitor(s) with care to avoid additional ESR and/or ESL. GND and PGND (Power GND) should be isolated, with a single point connection between them. D In order to effectively remove heat from the package, prepare thermal land and solder to the package’s thermal pad. Wide trace of the component−side copper, connected to this thermal land, will help heat spreading. Numerous vias 0.33 mm in diameter connected from the thermal land to the internal/solder−side ground plane(s) should be used to help dissipation. (4) |
Numéro de pièce similaire - TPS51100_07 |
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Description similaire - TPS51100_07 |
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