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TP5335 Fiches technique(PDF) 1 Page - Supertex, Inc

No de pièce TP5335
Description  P-Channel Enhancement-Mode Vertical DMOS FET
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Fabricant  SUTEX [Supertex, Inc]
Site Internet  http://www.supertex.com
Logo SUTEX - Supertex, Inc

TP5335 Fiches technique(HTML) 1 Page - Supertex, Inc

  TP5335_07 Datasheet HTML 1Page - Supertex, Inc TP5335_07 Datasheet HTML 2Page - Supertex, Inc TP5335_07 Datasheet HTML 3Page - Supertex, Inc  
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TP5335
Features
High input impedance and high gain
Low power drive requirement
Ease of paralleling
Low C
ISS and fast switching speeds
Excellent thermal stability
Integral source-drain diode
Free from secondary breakdown
Complementary N- and P-channel devices
Applications
Logic level interfaces - ideal for TTL and CMOS
Solid state relays
Analog switches
Power management
Telecom switches
General Description
The Supertex
TP5335 is a low threshold enhancement-
mode (normally-off) transistor utilizing an advanced vertical
DMOS structure and Supertex’s well-proven silicon-gate
manufacturing process. This combination produces a device
with the power handling capabilities of bipolar transistors
and the high input impedance and positive temperature
coefficient inherent in MOS devices. Characteristic of all
MOS structures, this device is free from thermal runaway
and thermally-induced secondary breakdown.
Supertex’s vertical DMOS FETs are ideally suited to a
wide range of switching and amplifying applications where
high breakdown voltage, high input impedance, low input
capacitance, and fast switching speeds are desired.
Absolute Maximum Ratings
Parameter
Value
Drain-to-source voltage
BV
DSS
Drain-to-gate voltage
BV
DGS
Gate-to-source voltage
±20V
Operating and storage
temperature
-55OC to +150OC
Soldering temperature*
300OC
Absolute Maximum Ratings are those values beyond which damage to the device may
occur. Functional operation under these conditions is not implied. Continuous operation
of the device at the absolute rating level may affect device reliability. All voltages are
referenced to device ground.
*Distance of 1.6mm from case for 10 seconds.
Ordering Information
BV
DSs/
BV
DGs
R
DS(ON)
(max)
V
GS(TH)
(max)
Package Options
TO-236AB
-350V
30Ω
-2.4V
TP5335K1
TP5335K1-G
-G indicates package is RoHS compliant (‘Green’)
P-Channel Enhancement-Mode
Vertical DMOS FET
Pin Configuration
TO-236AB
(Top View)
Gate
Source
Drain
Product Marking Information
Product marking for SOT-23:
where
= 2-week alpha date code
Underline indicates Pb-Free (”Green”)
P3S


Numéro de pièce similaire - TP5335_07

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