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SN74GTLP1394RGYR Fiches technique(PDF) 3 Page - Texas Instruments |
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SN74GTLP1394RGYR Fiches technique(HTML) 3 Page - Texas Instruments |
3 / 25 page www.ti.com FUNCTION TABLES OEAB T/C OEBY 7 9 1 ERC 8 A1 5 Y1 2 VREF 10 A2 6 Y2 3 B1 14 B2 12 SN74GTLP1394 2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY SCES286F – OCTOBER 1999 – REVISED APRIL 2005 OUTPUT CONTROL INPUTS OUTPUT MODE T/C OEAB OEBY X H H Z Isolation H L H A data to B bus True transparent H H L B data to Y bus True transparent with H L L A data to B bus, B data to Y bus feedback path L L H Inverted A data to B bus Inverted transparent L H L Inverted B data to Y bus Inverted A data to B bus, Inverted transparent with L L L Inverted B data to Y bus feedback path OUTPUT EDGE-RATE CONTROL (ERC) INPUT ERC OUTPUT B-PORT LOGIC NOMINAL EDGE RATE LEVEL VOLTAGE L GND Slow H VCC Fast LOGIC DIAGRAM (POSITIVE LOGIC) 3 |
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