Moteur de recherche de fiches techniques de composants électroniques
  French  ▼
ALLDATASHEET.FR

X  

SN74GTLP1394 Fiches technique(PDF) 5 Page - Texas Instruments

Click here to check the latest version.
No de pièce SN74GTLP1394
Description  2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
Download  25 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Fabricant  TI [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI - Texas Instruments

SN74GTLP1394 Fiches technique(HTML) 5 Page - Texas Instruments

  SN74GTLP1394 Datasheet HTML 1Page - Texas Instruments SN74GTLP1394 Datasheet HTML 2Page - Texas Instruments SN74GTLP1394 Datasheet HTML 3Page - Texas Instruments SN74GTLP1394 Datasheet HTML 4Page - Texas Instruments SN74GTLP1394 Datasheet HTML 5Page - Texas Instruments SN74GTLP1394 Datasheet HTML 6Page - Texas Instruments SN74GTLP1394 Datasheet HTML 7Page - Texas Instruments SN74GTLP1394 Datasheet HTML 8Page - Texas Instruments SN74GTLP1394 Datasheet HTML 9Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 5 / 25 page
background image
www.ti.com
Recommended Operating Conditions
(1) (2) (3) (4)
SN74GTLP1394
2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
SCES286F – OCTOBER 1999 – REVISED APRIL 2005
MIN
NOM
MAX
UNIT
VCC,
Supply voltage
3.15
3.3
3.45
V
BIAS VCC
GTL
1.14
1.2
1.26
VTT
Termination voltage
V
GTLP
1.35
1.5
1.65
GTL
0.74
0.8
0.87
VREF
Reference voltage
V
GTLP
0.87
1
1.1
B port
VTT
VI
Input voltage
V
Except B port
VCC
5.5
B port
VREF + 0.05
VIH
High-level input voltage
ERC
VCC – 0.6
VCC
5.5
V
Except B port and ERC
2
B port
VREF – 0.05
VIL
Low-level input voltage
ERC
GND
0.6
V
Except B port and ERC
0.8
IIK
Input clamp current
–18
mA
IOH
High-level output current
Y outputs
–24
mA
Y outputs
24
IOL
Low-level output current
mA
B port
100
∆t/∆v
Input transition rise or fall rate
Outputs enabled
10
ns/V
∆t/∆V
CC
Power-up ramp rate
20
µs/V
TA
Operating free-air temperature
–40
85
°C
(1)
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
(2)
Proper connection sequence for use of the B-port I/O precharge feature is GND and BIAS VCC = 3.3 V first, I/O second, and VCC = 3.3 V
last, because the BIAS VCC precharge circuitry is disabled when any VCC pin is connected. The control and VREF inputs can be
connected anytime, but normally are connected during the I/O stage. If B-port precharge is not required, any connection sequence is
acceptable, but generally, GND is connected first.
(3)
VTT and RTT can be adjusted to accommodate backplane impedances if the dc recommended IOL ratings are not exceeded.
(4)
VREF can be adjusted to optimize noise margins, but normally is two-thirds VTT. TI-OPC circuitry is enabled in the A-to-B direction and is
activated when VTT > 0.7 V above VREF. If operated in the A-to-B direction, VREF should be set to within 0.6 V of VTT to minimize current
drain.
5


Numéro de pièce similaire - SN74GTLP1394

FabricantNo de pièceFiches techniqueDescription
logo
Texas Instruments
SN74GTLP1394 TI-SN74GTLP1394 Datasheet
143Kb / 9P
[Old version datasheet]   2-BIT LVTTL-TO-GTL ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SELECTABLE POLARITY
SN74GTLP1394 TI1-SN74GTLP1394 Datasheet
890Kb / 23P
[Old version datasheet]   2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
SN74GTLP1394D TI-SN74GTLP1394D Datasheet
143Kb / 9P
[Old version datasheet]   2-BIT LVTTL-TO-GTL ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SELECTABLE POLARITY
SN74GTLP1394D TI1-SN74GTLP1394D Datasheet
890Kb / 23P
[Old version datasheet]   2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
SN74GTLP1394DGV TI-SN74GTLP1394DGV Datasheet
143Kb / 9P
[Old version datasheet]   2-BIT LVTTL-TO-GTL ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SELECTABLE POLARITY
More results

Description similaire - SN74GTLP1394

FabricantNo de pièceFiches techniqueDescription
logo
Texas Instruments
SN74GTLP1394 TI1-SN74GTLP1394_15 Datasheet
890Kb / 23P
[Old version datasheet]   2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
SN74GTLP1395 TI-SN74GTLP1395 Datasheet
443Kb / 21P
[Old version datasheet]   TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
SN74GTLP21395 TI-SN74GTLP21395 Datasheet
438Kb / 21P
[Old version datasheet]   TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
SN74GTLP22033 TI1-SN74GTLP22033 Datasheet
645Kb / 21P
[Old version datasheet]   8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SN74GTLP22034 TI-SN74GTLP22034 Datasheet
366Kb / 20P
[Old version datasheet]   8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SN74GTLP2033 TI-SN74GTLP2033 Datasheet
367Kb / 15P
[Old version datasheet]   8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SN74GTLP2034 TI-SN74GTLP2034 Datasheet
435Kb / 21P
[Old version datasheet]   8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH
logo
Fairchild Semiconductor
GTLP10B320 FAIRCHILD-GTLP10B320 Datasheet
261Kb / 12P
   10-Bit LVTTL/GTLP Transceiver with Split LVTTL Port and Feedback Path
GTLP1B151 FAIRCHILD-GTLP1B151 Datasheet
112Kb / 7P
   1-Bit LVTTL/GTLP Transceiver with Separate LVTTL Port and Feedback Path
logo
Texas Instruments
SN74GTLP1394 TI-SN74GTLP1394 Datasheet
143Kb / 9P
[Old version datasheet]   2-BIT LVTTL-TO-GTL ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SELECTABLE POLARITY
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25


Fiches technique Télécharger

Go To PDF Page


Lien URL




Politique de confidentialité
ALLDATASHEET.FR
ALLDATASHEET vous a-t-il été utile ?  [ DONATE ] 

À propos de Alldatasheet   |   Publicité   |   Contactez-nous   |   Politique de confidentialité   |   Echange de liens   |   Fabricants
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com