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SM65MLVD082DGGR Fiches technique(PDF) 1 Page - Texas Instruments

No de pièce SM65MLVD082DGGR
Description  8-CHANNEL HALF-DUPLEX M-LVDS LINE TRANSCEIVERS
Download  28 Pages
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Fabricant  TI [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI - Texas Instruments

SM65MLVD082DGGR Fiches technique(HTML) 1 Page - Texas Instruments

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FEATURES
APPLICATIONS
DESCRIPTION
LOGIC DIAGRAM (POSITIVE LOGIC)
1DE
1D
RE
1R
1A
1B
SN65MLVD080, SN65MLVD082
Channel 1
Channels 2 - 8
7
7
7
2DE - 8DE
2D - 8D
2R - 8R
2A - 8A
2B - 8B
SN65MLVD080
SN65MLVD082
SLLS581B – SEPTEMBER 2003 – REVISED SEPTEMBER 2005
8-CHANNEL HALF-DUPLEX M-LVDS LINE TRANSCEIVERS
The M-LVDS standard defines two types of receivers,
designated as Type-1 and Type-2. Type-1 receivers
Low-Voltage Differential 30-
Ω to 55-Ω Line
(SN65MLVD080) have thresholds centered about
Drivers and Receivers for Signaling Rates (1)
zero with 25 mV of hysteresis to prevent output
Up to 250 Mbps; Clock Frequencies Up to
oscillations with loss of input; Type-2 receivers
125 MHz
(SN65MLVD082) implement a failsafe by using an
Meets or Exceeds the M-LVDS Standard
offset threshold. In addition, the driver rise and fall
times are between 1 and 2.0 ns, complying with the
TIA/EIA-899 for Multipoint Data Interchange
M-LVDS standard to provide operation at 250 Mbps
Controlled Driver Output Voltage Transition
while also accommodating stubs on the bus. Receiver
Times for Improved Signal Quality
outputs are slew rate controlled to reduce EMI and
–1 V to 3.4 V Common-Mode Voltage Range
crosstalk effects associated with large current surges.
Allows Data Transfer With 2 V of Ground
The M-LVDS standard allows for 32 nodes on the bus
Noise
providing a high-speed replacement for RS-485
where lower common-mode can be tolerated or when
Bus Pins High Impedance When Driver
higher signaling rates are needed.
Disabled or V
CC ≤ 1.5 V
The driver logic inputs and the receiver logic outputs
Independent Enables for each Driver
are on separate pins rather than tied together as in
Bus Pin ESD Protection Exceeds 8 kV
some transceiver designs. The drivers have separate
Packaged in 64-Pin TSSOP (DGG)
enables (DE) and the receivers are enabled globally
through (RE). This arrangement of separate logic
M-LVDS Bus Power Up/Down Glitch Free
inputs, logic outputs, and enable pins allows for a
listen-while-talking
operation.
The
devices
are
characterized for operation from –40
°C to 85°C.
Parallel Multipoint Data and Clock
Transmission Via Backplanes and Cables
Low-Power High-Speed Short-Reach
Alternative to TIA/EIA-485
Cellular Base Stations
Central-Office Switches
Network Switches and Routers
The SN65MLVD080 and SN65MLVD082 provide
eight half-duplex transceivers for transmitting and
receiving Multipoint-Low-Voltage Differential Signals
in full compliance with the TIA/EIA-899 (M-LVDS)
standard, which are optimized to operate at signaling
rates up to 250 Mbps. The driver outputs have been
designed to support multipoint buses presenting
loads as low as 30-
Ω and incorporates controlled
transition times to allow for stubs off of the backbone
transmission line.
(1)
The signaling rate of a line, is the number of voltage
transitions that are made per second expressed in the units
bps (bits per second).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2003–2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.


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