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SI5323-B-GM Fiches technique(PDF) 7 Page - Silicon Laboratories |
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SI5323-B-GM Fiches technique(HTML) 7 Page - Silicon Laboratories |
7 / 16 page Si5323 Preliminary Rev. 0.2 7 2. Pin Descriptions: Si5323 Pin assignments are preliminary and subject to change. 1 2 3 29 30 31 32 33 34 35 36 20 21 22 23 24 25 26 27 10 11 12 13 14 15 16 17 4 5 6 7 8 FRQTBL AUTOSEL RST C2B C1B GND VDD XA CS_CA BWSEL0 BWSEL1 FRQSEL1 FRQSEL2 FRQSEL3 GND Pad FRQSEL0 INC 9 18 19 28 XB DEC Table 3. Si5323 Pin Descriptions Pin # Pin Name I/O Signal Level Description 1RST ILVCMOS External Reset. Active low input that performs external hardware reset of device. Resets all internal logic to a known state. Clock out- puts are tristated during reset. After rising edge of RST sig- nal, the Si5323 will perform an internal self-calibration. This pin has a weak pull-up. 2 FRQTBL I 3-Level Frequency Table Select. Selects SONET/SDH, datacom, or SONET/SDH to datacom frequency table. L=SONET/SDH M = Datacom H = SONET/SDH to Datacom This pin has a weak pull-down. 3C1B O LVCMOS CKIN1 Loss of Signal. Active high loss-of-signal indicator for CKIN1. Once trig- gered, the alarm will remain active until CKIN1 is validated. 0 = CKIN1 present 1 = LOS on CKIN1 4C2B O LVCMOS CKIN2 Loss of Signal. Active high loss-of-signal indicator for CKIN2. Once trig- gered, the alarm will remain active until CKIN2 is validated. 0 = CKIN2 present 1 = LOS on CKIN2 |
Numéro de pièce similaire - SI5323-B-GM |
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Description similaire - SI5323-B-GM |
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