LC87F14C8A

No.A0402-3/26

Continued from preceding page.

• SIO9: Synchronous serial interface

1) LSB first/MSB first mode selectable

2) Transfer clock cycle: 4/3 to 1020/3 tCYC

3) Automatic continuous data transmission (1 to 4096 bytes, specifiable in 1 byte units, suspension and resumption

of data transmission possible in 1 byte or 2 bytes units)

4) Auto-start-on-falling-edge function

5) Clock polarity selectable

6) CRC16 calculator circuit built in

Full Duplex UART

• UART1

1) Data length: 7/8/9 bits selectable

2) Stop bits: 1 bit (2 bits in continuous transmission mode)

3) Baud rate: 16/3 to 8192/3 tCYC

AD Converter: 8 bits

× 12 channels

PWM: Multifrequency 12-bit PWM

× 2 channels

USB Interface (host controller)

• Full-Speed is supported

• Transfer type: Control, Bulk, Interrupt, or Isochronous transfer possible

Watchdog Timer

• External RC watchdog timer

• Interrupt and reset signals selectable

Clock Output Function

1) Able to output selected oscillation clock 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 as system clock.

2) Able to output oscillation clock of sub clock.

Interrupts

• 36 sources, 10 vector addresses

1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of

the level equal to or lower than the current interrupt are not accepted.

2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level

takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector

address takes precedence.

No.

Vector Address

Level

Interrupt Source

1

00003H

X or L

INT0

2

0000BH

X or L

INT1

3

00013H

H or L

INT2 / T0L / INT4/ UHC bus active

4

0001BH

H or L

INT3 / INT5 / base timer

5

00023H

H or L

T0H/ INT6 / UHC device attach / UHC device detach / UHC resume

6

0002BH

H or L

T1L / T1H / INT7 / SIO9

7

00033H

H or L

SIO0 / UART1 receive

8

0003BH

H or L

SIO1 / SIO4 / UART1 transmit

9

00043H

H or L

ADC / T6 / T7 / UHC-ACK / UHC-NAK / UHC error / UHC STALL

10

0004BH

H or L

Port 0 / PWM0 / PWM1 / T4 / T5 / UHC-SOF

• Priority levels X > H > L

• Of interrupts of the same level, the one with the smallest vector address takes precedence.

Subroutine Stack Levels: 5120 levels (the stack is allocated in RAM.)