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AM79C864A Fiches technique(PDF) 1 Page - Advanced Micro Devices |
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AM79C864A Fiches technique(HTML) 1 Page - Advanced Micro Devices |
1 / 51 page Publication# 15535 Rev. B Amendment /0 Issue Date: November 1993 This document contains information on a product under development at Advanced Micro Devices, Inc. The information is intended to help you to evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. 3-3 Advanced Micro Devices Am79C864A Physical Layer Controller With Scrambler (PLC-S) PRELIMINARY DISTINCTIVE CHARACTERISTICS s Implements FDDI PHY layer protocol for ISO standard (FDDI) 9314-1 s Implements ANSI standard Stream Cipher Scrambling/Descrambling s Hardware Physical Connection Management (PCM) support s Performs Physical Connection insertion and removal s On-chip Link Error Monitor (LEM) and Link Confidence Test (LCT) s Line state detection s Repeat filter s Elasticity buffer and smoother functions s 4B/5B encoding/decoding s Full duplex operation s Data framing s Built-in Self Test GENERAL DESCRIPTION The Physical Layer Controller with Scrambler (PLC-S) is a CMOS device which along with Physical Data Transmitter (PDT) and Physical Data Receiver (PDR) implements the Physical Layer Protocol (PHY) and por- tions of the Station Management (SMT) of the ANSI Fi- ber Distributed Data Interface (FDDI) standard. The PLC-S, PDT and PDR are collectively known as the AmPHY. PHY functions performed by the PLC-S in- clude framing of data on symbol pair boundaries, the elasticity buffer function, the smoothing function, 4B/5B encoding and decoding of symbols, line state detection, the repeat filter function, and Stream Cipher Scram- bling/Descrambling. SMT functions performed include Physical Connection Management (PCM), Physical Connection insertion and removal and Link Error Monitor. The PLC-S chip receives symbol-wide (5 bits) data along with a 25 MHz recovered clock from the PDR chip and searches for a JK symbol pair (also known as Start- ing Delimiter). It uses the starting delimiter to establish byte boundaries (i.e. to frame the data). Framed data is then sent to the Elasticity Buffer which serves to compensate for the frequency difference be- tween the recovered clock and the local clock. Data out- put by the Elasticity Buffer is checked by the Smoother and when necessary, Idle symbols are inserted be- tween frames to maintain a minimum number of Idle symbols in the interframe gap. The data is then decoded and sent to the Media Access Control (MAC) chip. The data is byte-wide (10 bits) and is clocked by a 12.5 MHz local clock. The PLC-S receives byte-wide data from the MAC at 12.5 million bytes per second, encodes the data and sends out symbol-wide data at 25 million symbols per second to PDT chip. In the transmit path, there is a Re- peat Filter to detect corrupted symbols and convert them into the specified pattern of Halt and Idle symbols. The Repeat Filter in each PLC-S chip converts the last byte of a frame fragment into Idle symbols and thus eventually removing fragments from the ring. The PLC-S device includes a Stream Cipher Scrambler/ Descrambler as prescribed in the ANSI TP-PMD stan- dard for transmission over twisted-pair cable. For copper-based designs, the scrambler/descrambler may be enabled either through software or hardware. For fi- ber-based designs, the scrambler/descrambler is dis- abled by default. For a detailed description of the ANSI-compliant copper FDDI system using the PLC-S device, refer to AMD PID #18258A, Implementing FDDI over Copper; The ANSI X3T9.5 Standard. The PCM initializes the connection of neighboring PHYs and manages the PHY signaling. PCM consists of the PCM state machine, which determines the timing and state requirements for PCM, and the PCM Pseudo Code, which provides the information to be communi- cated to the neighboring PCM and specifies the connec- tion policies. The PLC-S chip contains the PCM State Machine, while the PCM Pseudo Code is controlled by software. The PCM State Machine communicates with other PCMs using a bit signaling mechanism whereby certain line states are received and transmitted. The PCM also makes use of the Link Error Monitor in the |
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