CY7B9973V datasheet(1/8 Pages) CYPRESS

No de pièce	CY7B9973V

Description	High-Speed Multi-Output PLL Clock Buffer

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Fabricant	CYPRESS [Cypress Semiconductor]

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High-Speed Multi-Output PLL Clock Buffer

RoboClock®

CY7B9973V

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

, CA 95134

•

408-943-2600

Document #: 38-07430 Rev. *B

Revised September 27, 2006

Features

• 10-MHz – 200-MHz output operation

• Output-to-output skews < 350 ps

• 13 LVTTL 50% duty-cycle outputs capable of driving

50

Ω terminated lines

• Phase-locked loop (PLL) LOCK indicator

• 3.3V LVTTL/LV differential (LVPECL) hot insertable

reference inputs

• Multiply/divide ratios of (4, 6, 8, 10, 12, 16, 20):(2, 4, 6,

8, 10, 12, 16, 20)

• Operation with outputs operating at up to 10x input

frequency

• Low cycle-to-cycle jitter (< ±75 ps peak-peak)

• Single 3.3V ± 10% supply

• Pin-compatible with Motorola MPC973

• 52-pin TQFP package

Functional Description

The CY7B9973V Low-Voltage PLL Clock Buffer offers

user-selectable frequency control over system clock functions.

This twelve output clock driver provides the system integrator

selectable frequency ratios of 1:1, 2:1, 3:1, 3:2, 4:3, 5:1, 5:2,

5:3, 6:1 and 6:5 between outputs. An additional output is

dedicated to providing feedback information to allow the

internal PLL to multiply an external reference frequency by 4,

6, 8, 10, 12, 16 or 20. The completely integrated PLL reduces

jitter and simplifies board layout.

The thirteen configurable outputs can each drive terminated

transmission lines with impedances as low as 50

Ω while deliv-

ering minimal and specified output skews at LVTTL levels.

The CY7B9973V has a flexible reference input scheme with

three different hot-insertion capable inputs. These inputs allow

the use of either differential LVPECL or single-ended LVTTL

inputs which can be dynamically selected to provide the

reference frequency.

D Q

0

1

÷2

÷4, ÷6, ÷8, ÷12

÷4, ÷6, ÷8, ÷10

÷2, ÷4, ÷6, ÷8

÷4, ÷6, ÷8, ÷10

Data Generator

LOCK (25)

Qa0 (50)

Qa1 (48)

Qa2 (46)

Qa3 (44)

Qb0 (38)

Qb1 (36)

Qb2 (34)

Qb3 (32)

Qc0 (23)

Qc1 (21)

Qc2 (18)

Qc3 (16)

QFB (29)

LPF

PHASE

DETECTOR

1

0

1

2

Inv_Clk (14)

fselFB0:1 (27,26)

fselc0:1 (20,19)

fselb0:1 (41,40)

fsela0:1 (43,42)

MR/OE (2)

fselFB2 (5)

Ext_FB (31)

TCLK1 (10)

TCLK0 (9)

TCLK_Sel (8)

Ref_Sel (7)

PLL_En (6)

PECL_CLK (12)

PECL_CLK (11)

VCO_Sel (52)

Reset

VCO

0

1

÷2/÷1

Logic Diagram

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