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MC100ES6056DT Fiches technique(PDF) 4 Page - Integrated Device Technology |
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MC100ES6056DT Fiches technique(HTML) 4 Page - Integrated Device Technology |
4 / 9 page MC100ES6056 3.3V, 2.5VECL/LVPECL/LVDS DUAL DIFFERENTIAL 2:1 MULTIPLEXER ADVANCED CLOCK DRIVERS DEVICES IDT™ / ICS™ 2:1 MULTIPLEXER 4 MC100ES6056 REV. 5 JULY 16, 2007 Figure 1 Figure 2. Typical Termination for Output Driver and Device Evaluation Table 6. AC Characteristics (VCC = 0 V; VEE = –2.5 V ± 5% or –3.8 V to –3.135 V; VCC = 2.5 V ± 5% or 3.135 V to 3.8 V; VEE = 0 V)(1) 1. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 Ω to VCC–2.0 V. Symbol Characteristics –40°C to 85°C Unit Min Typ Max fmax Maximum Frequency > 3 GHz tPLH, tPHL Propagation Delay to Output Differential D to Q, Q SEL to Q, Q COM_SEL to Q, Q 300 300 300 400 430 490 500 600 650 ps ps ps tSKEW Skew Output-to-Output(2) Part-to-Part 2. Skew is measured between outputs under identical transitions. Duty cycle skew is defined only for differential operation when the delays are measured from the cross point of the inputs to the cross point of the outputs. 10 50 200 ps ps tJITTER Cycle-to-Cycle Jitter RMS (1 σ) 1 ps VPP Minimum Input Swing 200 800 1200 mV VCMR Differential Cross Point Voltage VCC–2.1 VCC–1.1 V tr / tf Output Rise/Fall Time (20%–80%) 70 120 230 ps Driver Device Receiver Device QD D Q 50 Ω 50 Ω VTT VTT = VCC – 2.0 V |
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