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SA5522 Fiches technique(PDF) 6 Page - NXP Semiconductors |
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SA5522 Fiches technique(HTML) 6 Page - NXP Semiconductors |
6 / 20 page 1996 Jan 23 6 Philips Semiconductors Product specification 1.4 GHz I2C-bus controlled synthesizer TSA5522 FUNCTIONAL DESCRIPTION The device is controlled via the two-wire I2C-bus. For programming, there is one module address (7 bits) and the R/W bit for selecting the READ or the WRITE mode. I2C-bus mode WRITE MODE (R/W = 0); see Table 1 Data bytes can be sent to the device after the address transmission (first byte). Four data bytes are required to fully program the device. The bus transceiver has an auto-increment facility which permits the programming of the device within one single transmission (address + 4 data bytes). The device can also be partially programmed providing that the first data byte following the address is divider byte 1 (DB1) or control byte (CB). The bits in the data bytes are defined in Table 1. The first bit of the first data byte transmitted indicates whether frequency data (first bit = 0) or control and ports data (first bit = 1) will follow. Until an I2C-bus STOP command is sent by the controller, additional data bytes can be entered without the need to re-address the device. The frequency register is loaded after the 8th clock pulse of the second divider byte (DB2), the control register is loaded after the 8th clock pulse of the control byte (CB) and the ports register is loaded after the 8th clock pulse of the ports byte (PB). I2C-BUS ADDRESS SELECTION The module address contains programmable address bits (MA1 and MA0) which offer the possibility of having several synthesizers (up to 3) in one system by applying a specific voltage on the AS input. The relationship between MA1 and MA0 and the input voltage on the AS input is given in Table 3. Table 1 I2C-bus data format Note 1. Not available on 16-pin devices. Table 2 Description of Table 1 BYTE MSB DATA BYTE LSB COMMAND Address byte (ADB) 1 1 0 0 0 MA1 MA0 0 A Divider byte 1 (DB1) 0 N14 N13 N12 N11 N10 N9 N8 A Divider byte 2 (DB2) N7 N6 N5 N4 N3 N2 N1 N0 A Control byte (CB) 1 CP T2 T1 T0 RSA RSB OS A Ports byte (PB) P7(1) P6 P5(1) P4(1) XP2 P1 P0 A SYMBOL DESCRIPTION MA1, MA0 programmable address bits (see Table 3) N14 to N0 programmable divider bits N = N14 × 214 + N13 × 213 + ... + N1 × 2 + N0 CP charge-pump current; CP = 0 = 50 µA; CP = 1 = 250 µA T2 to T0 test bits (see Table 4). For normal operation T2 = 0; T1 = 0; T0 = 1 RSA, RSB reference divider ratio select bits (see Table 5) OS tuning amplifier control bit; for normal operation OS = 0 and tuning voltage is ON; when OS = 1 tuning voltage is OFF (high impedance) P2 to P0 PNP band switch buffers control bits P7 to P4 NPN open collector control bits when Pn = 0 output n is OFF; when Pn = 1 output n is ON X don’t care |
Numéro de pièce similaire - SA5522 |
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Description similaire - SA5522 |
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