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TSA5522 Fiches technique(PDF) 7 Page - NXP Semiconductors

No de pièce TSA5522
Description  1.4 GHz I2C-bus controlled synthesizer
Download  20 Pages
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Fabricant  PHILIPS [NXP Semiconductors]
Site Internet  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

TSA5522 Fiches technique(HTML) 7 Page - NXP Semiconductors

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1996 Jan 23
7
Philips Semiconductors
Product specification
1.4 GHz I2C-bus controlled synthesizer
TSA5522
Table 3
Address selection
Table 4
Test bits
Table 5
Ratio select bits
Table 6
Band switch output levels
VOLTAGE APPLIED ON AS
INPUT
MA1
MA2
0 to 0.1VCC1
00
Always valid
0
1
0.4VCC1 to 0.6VCC1
10
0.9VCC1 to VCC1
11
T2
T1
T0
DEVICE OPERATION
0
0
1
normal mode
0
1
X
charge-pump is OFF
1
1
0
charge-pump is sinking current
1
1
1
charge-pump is sourcing current
100
fref is available at LOCK output
101
1
2fdiv is available at LOCK output
RSA
RSB
REFERENCE DIVIDER
X
0
640
0
1
1024
1
1
512
P2
P1
P0
VOLTAGE
ON BS
OUTPUT
PHILIPS M/O
BAND
0
1
0
0.25 V
band A
1
0
0
0.4VCC1
band B
0
0
1
0.8VCC1
band C
READ MODE; R/W = 1 (see Table 7)
Data can be read from the device by setting the R/W bit to
logic 1. After the slave address has been recognized, the
device generates an acknowledge pulse and the first data
byte (status byte) is transferred on the SDA line (MSB
first). Data is valid on the SDA line during a HIGH level of
the SCL clock signal. A second data byte can be read from
the device if the microcontroller generates an
acknowledge on the SDA line (master acknowledge). End
of transmission will occur if no master acknowledge
occurs. The device will then release the data line to allow
the microcontroller to generate a STOP condition. When
ports P4 to P7 are used as inputs, the corresponding bits
must be logic 0 (high impedance state). The POR flag is
set to logic 1 at power-on. The flag is reset when an
end-of-data is detected by the device (end of a read
sequence). Control of the loop is made possible with the
in-lock flag (FL) which indicates when the loop is locked
(FL = 1).
The bits I2, to I0 represent the status of the I/O ports
P7, P5 and P4 respectively. A logic 0 indicates a LOW
level and a logic 1 indicates a HIGH level
(see “Characteristics”).
A built-in ADC is available at pin P6. This converter can be
used to apply AFC information to the microcontroller from
the IF section of the television. The relationship between
the bits A2 to A0 is given in Table 8.
Table 7
READ data format
Notes
1. A = acknowledge.
2. POR = power-on-reset (POR = 1 at power-on).
3. FL = in-lock flag (FL = 1 when loop is locked).
4. I2 to I0 = digital levels for I/O ports P7, P5 and P4 respectively.
5. A2 to A0 = digital outputs of the 5-level ADC.
BYTE
MSB
DATA BYTE
LSB
COMMAND
Address byte (ADB)
11000
MA1
MA0
1
A(1)
Status byte (SB)
POR(2)
FL(3)
I2(4)
I1(4)
I0(4)
A2(5)
A1(5)
A0(5)


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