August 1982

11

Philips Semiconductors

Product specification

Control circuit for switched-mode power supply

TEA1039

Fig.6

the frequency regulation mode as a function of external resistor R4 connected between RX and ground

with external capacitor C5 connected between CX and ground as a parameter.

Fig.7

Timing diagram for the duty factor regulation mode showing the voltage on external capacitor C5

connected between CX and ground and the output voltage as a function of time for two combinations of

input signals.

a: The voltages on inputs FB or LIM are below 5,9 V. The circuit is in its normal regulation

range.

b: The voltages on inputs FB and LIM are higher than 5,9 V. The circuit produces its minimum

output LOW time, giving the maximum duty factor of the SMPS.