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TDA9850 Fiches technique(PDF) 7 Page - NXP Semiconductors |
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TDA9850 Fiches technique(HTML) 7 Page - NXP Semiconductors |
7 / 32 page 1995 Jun 19 7 Philips Semiconductors Preliminary specification I2C-bus controlled BTSC stereo/SAP decoder TDA9850 FUNCTIONAL DESCRIPTION Input level adjustment The composite input signal is fed to the input level adjustment stage. The control range is from −3.5 to +4.0 dB in steps of 0.5 dB. The subaddress control 4 of Tables 5 and 6 and the level adjust setting of Table 10 allows an optimum signal adjustment during the set alignment. The maximum input signal voltage is 2 V (RMS). Stereo decoder The output signal of the level adjustment stage is coupled to a low-pass filter which suppresses the baseband noise above 125 kHz. The composite signal is then fed into a pilot detector/pilot cancellation circuit and into the MPX demodulator. The main L + R signal passes a 75 µs fixed de-emphasis filter and is fed into the dematrix circuit. The decoded sub-signal L − R is sent to the stereo/SAP switch. To generate the pilot signal the stereo demodulator uses a PLL circuit including a ceramic resonator. The stereo channel separation is adjusted by an automatic procedure to be performed during set production. For a detailed description see Section “Adjustment procedure”. The stereo identification can be read by the I2C-bus (see Table 2). Two different pilot thresholds (data STS = 1; STS = 0) can be selected via the I2C-bus (see Table 14). SAP demodulator The composite signal is fed from the output of the input level adjustment stage to the SAP demodulator circuit through a 5fH band-pass filter. The demodulator level is automatically controlled. The SAP demodulator includes an internal field strength detector that mutes the SAP output in the event of insufficient signal conditions. The SAP identification signal can be read by the I2C-bus (see Table 2). Noise detector The composite input noise increases with decreasing antenna signal. This makes it necessary to switch stereo or SAP off at certain thresholds. These thresholds can be set via the I2C-bus. With ST0 to ST3 (see Table 6) the stereo threshold can be selected and with SP0 to SP3 the SAP threshold. A hysteresis can be achieved via software by making the threshold dependent of the identification bits STP and SAPP (see Table 2). Mode selection The stereo/SAP switch feeds either the L − R signal or the SAP demodulator output signal via the internal dbx noise reduction circuit to the dematrix/switching circuit. Table 8 shows the different switch modes provided at the output pins OUTR and OUTL. dbx decoder The dbx circuit includes all blocks required for the noise reduction system in accordance with the BTSC system specification. The output signal is fed through a 73 µs fixed de-emphasis circuit to the dematrix block. SAP output Independent of the stereo/SAP switch, the SAP signal is also available at pin SAP. At SAP, the SAP signal is not dbx decoded. The capacitor at SDE provides a recommended de-emphasis (150 µs) at SAP. Integrated filters The filter functions necessary for stereo and SAP demodulation and part of the dbx filter circuits are provided on-chip using transconductor circuits. The required filter accuracy is attained by an automatic filter alignment circuit. |
Numéro de pièce similaire - TDA9850 |
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Description similaire - TDA9850 |
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