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ST8004 Fiches technique(PDF) 11 Page - STMicroelectronics

No de pièce ST8004
Description  Smartcard interface
Download  26 Pages
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Fabricant  STMICROELECTRONICS [STMicroelectronics]
Site Internet  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST8004 Fiches technique(HTML) 11 Page - STMicroelectronics

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ST8004
Electrical characteristics
11/26
Note:
1
To meet these specifications VCC should be decoupled to CGND using two ceramic
multiplier capacitors of low ESR with values of 100nF.
2
The transition time and duty cycle factor are shown in Figure 9.; d = t1/(t1+t2).
3
PRES and CMDVCC are active Low; RSTIN and PRES are active High
4
Referred to the paragraph "CLOCK CIRCUITRY"
5
See paragraph "FAULT DETECTION".
Table 14.
Logic inputs (pins CLKDIV1, CLKDIV2, PRES, PRES, CMDVCC, RSTIN and 5V/3V,
VTHSEL (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless otherwise noted. Typical values
are to Ta = 25°C) (Note 3)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
VIL
Low Level Input Voltage
0
0.3 VDD
V
VIH
High Level Input Voltage
0.7 VDD
VDD
V
|ILIH|
Input Leakage Current
when high
VIL = 0 to VDD
5µA
|ILIL|
Input Leakage Current
when low
VIH = 0 to VDD
5
µA
Table 15.
OFF outputs (pin OFF is an open drain with an internal 20 k
Pull-up resistor to VDD);
(see note 5) (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless otherwise noted. Typical values
are to TA = 25°C)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
VOL
Low Level Output Voltage
IOL = 2 mA
0.4
V
VOH
High Level Output Voltage
IOH = -15 µA
0.75 VDD
V
Table 16.
Protection (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless otherwise noted. Typical values
are to TA = 25°C)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
TSD
Shut down temperature
135
°C
ICC(SD)
Shut down current at VCC
150
mA
Table 17.
Timing (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless otherwise noted. Typical values are
to TA = 25°C)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
tACT
Activation sequence duration
(See
Figure 5.)180
220
µs
tDE
Deactivation sequence duration
(See
Figure 6.)60
80
100
µs
t3
Start of the windows to send
CLK to card
(See
Figure 5.)130
µs
t5
End of the windows to send
CLK to card
(See
Figure 5.)140
µs


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