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TDA10085 Fiches technique(PDF) 11 Page - NXP Semiconductors |
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TDA10085 Fiches technique(HTML) 11 Page - NXP Semiconductors |
11 / 16 page 2001 Aug 31 11 Philips Semiconductors Product specification Single chip DVB-S/DSS channel receiver TDA10085HT 10 APPLICATION INFORMATION handbook, full pagewidth 8 TDA10085HT VREFP VREFN VAGC 30 51-54 59-62 12 28 29 33 32 2 1 XIN XOUT DO[7-0] 50 OCLK 49 DEN 48 UNCOR 47 PSYNC SDA-0 SCL-0 SCL SDA MGU428 VIN2 GND 15 14 13 VIN1 PLL LO from LNB 90 ° PHASE SHIFT MIXER × MIXER × The TDA10085 can receive a 4 MHz clock signal delivered by the PLL synthesizer, or can generate the sampling clock from a crystal connected between XIN and XOUT. Bypass capacitors (0.1 µF) should be placed close to ADC voltage references VREFP and VREFN. Fig.3 Front-end receiver schematic. handbook, full pagewidth 8 TDA10085 TUNER channel I VIN1 VAGC 30 15 51-54 59-62 12 28 29 33 32 63 21 CTRL1 22K MPEG2 transport stream DO[7-0] SDA-0 SCL-0 SCL SDA MGU429 VIN2 channel Q LNB LNB SUPPLY GENERATION Fig.4 Typical use of CTRL1 and 22K outputs. |
Numéro de pièce similaire - TDA10085 |
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Description similaire - TDA10085 |
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