SAA7327 datasheet(54/68 Pages) PHILIPS

No de pièce	SAA7327

Description	Digital servo processor and Compact Disc decoder with integrated DAC for video CD CD7 II

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Fabricant	PHILIPS [NXP Semiconductors]

Site Internet	http://www.nxp.com

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54 / 68 page

1999 Jun 17

54

Philips Semiconductors

Product speciﬁcation

Digital servo processor and Compact Disc decoder

with integrated DAC for video CD (CD7 II)

SAA7327

10 OPERATING CHARACTERISTICS (SUBCODE INTERFACE TIMING)

VDD = 3.0 to 3.6 V; VSS = 0 V; Tamb = −10 to +70 °C; unless otherwise specified.

Note

1. The subcode timing is directly related to the overspeed factor ‘n’ in normal operating mode. ‘n’ is replaced by the disc

speed factor ‘d’, in lock-to-disc mode.

SYMBOL

PARAMETER

MIN.

TYP.

MAX.

UNIT

Subcode interface timing (single-speed

× n); see Fig.32; note 1

INPUT: PIN RCK

tCLKH

input clock HIGH time

2/n

4/n

6/n

µs

tCLKL

input clock LOW time

2/n

4/n

6/n

µs

tr

input clock rise time

−−

80/n

ns

tf

input clock fall time

−−

80/n

ns

td(SFSY-RCK)

delay time SFSY to RCK

10/n

−

20/n

µs

OUTPUTS: PINS SBSY, SFSY AND SUB (CL = 20 pF)

Tcy(block)

block cycle time

12.0/n

13.3/n

14.7/n

ms

tW(SBSY)

SBSY pulse width

−−

300/n

µs

Tcy(frame)

frame cycle time

122/n

136/n

150/n

µs

tW(SFSY)

SFSY pulse width (3-wire mode only)

−−

366/n

µs

tSFSYH

SFSY HIGH time

−−

66/n

µs

tSFSYL

SFSY LOW time

−−

84/n

µs

td(SFSY-SUB)

delay time SFSY to SUB (P data) valid

−−

1/n

µs

td(RCK-SUB)

delay time RCK falling to SUB

−−

0

µs

th(RCK-SUB)

hold time RCK to SUB

−−

0.7/n

µs

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