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SAA5250 Fiches technique(PDF) 5 Page - NXP Semiconductors |
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SAA5250 Fiches technique(HTML) 5 Page - NXP Semiconductors |
5 / 35 page January 1987 5 Philips Semiconductors Product specification Interface for data acquisition and control (for multi-standard teletext systems) SAA5250 PINNING FUNCTION MNEMONIC PIN NO. FUNCTION A10 and A0 to A9 1 and 30 to 39 Memory address outputs used by CIDAC to address a 2 K byte buffer memory VAL OUT 2 Validation output signal used to control the location of the window for the framing code. VAL IN/SYNC 3 Validation input signal (line signal) used to give or calculate a window for the framing code detection CBB 4 Colour burst blanking output signal used by the SAA5230 as a data slicer reset pulse DCK 5 Data clock input, in synchronization with the serial data signal SD 6 Serial data input, arriving from the demodulator MS 7 Chip enable output signal for buffer memory selection WE 8 Write command output for the buffer memory DB7 to DB0 9 to 16 8-bit three state input/output data/address bus used to transfer commands, data and status between the CIDAC registers and the CPU ALE 17 Demultiplexing input signal for the CPU data bus CE 18 Chip enable input for the SAA5250 WR 19 Write command input (when LOW) VSS 20 ground RD 21 Read command input (when LOW) D0 to D7 22 to 29 8-bit three state input/output data bus used to transfer data between CIDAC and the buffer memory VDD 40 +5 V power supply |
Numéro de pièce similaire - SAA5250 |
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Description similaire - SAA5250 |
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