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SA9025 Datasheet(Fiches technique) 17 Page - NXP Semiconductors

Numéro de pièce SA9025
Description  900 MHz transmit modulator and 2.2 GHz fractional-N synthesizer
Télécharger  23 Pages
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Fabricant  PHILIPS [NXP Semiconductors]
Site Internet  http://www.nxp.com
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 17 page
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Philips Semiconductors
Objective specification
SA9025
900 MHz transmit modulator and 2.2 GHz
fractional–N synthesizer
1997 Aug 01
17
MODES OF OPERATION
There are two power saving modes of operation which the circuit
can be put into, dependent on the status of the system. The
intention of these different modes is to disable circuitry that is not in
use at the time in order to reduce power consumption. During sleep
mode, only circuitry which is required to provide a master clock to
the digital portion of the system is enabled. During receive mode,
circuitry which is used to perform the receive function and provide a
master clock is enabled. In transmit mode all the functions of the
circuit are enabled which are required to perform transmit, receive
and provide master clock. When the circuit is powered for the first
time, it is in DUAL MODE SLEEP.
Mode Programming
Mode
Dual Mode AMPS
Mode Setting and BlockStatus (X = ON)
Sleep
RX
TX
Logic
TXEN
0
0
1
PD1
0
1
1
PD2
0
1
1
SE–>SYNen
0
0
1
TM
0
0
0
SM1
0
0
1
SM2
0
1
1
Main loop, Ndivider, RXLO buffer
X
X
PD1
Aux loop, Adivider
X
X
PD2
Rdivider
X
X
PD1 .OR. PD2
Offset VCO, Mdivider
X
SE (+delay) See
SE–>SYNEN diagram
RCL buffer
X
X
SM2
MCL buffer, reference input
X
X
X
1 (always ON)
DUALTX PA
X
(.not. TM) .and. TXEN
.and. SM1
TXLO buffer, SSB up–converter
X
SM1
I/Q MODULATOR, VGA
X
TXEN .AND. SM1
Control Logic
X
X
X
1 (always ON)
Main Divider
The input signal on RXLO is amplified to a logic level by a balanced
input comparator giving a common mode rejection. This input stage
is enabled by serial control bit PD1 = 1. Disabling means that all
currents in the comparator are switched off. The main divider is built
up to be a 16-bit counter.
The loading of the work registers FMOD, NF and NMAIN is
synchronized with the state of the main counter to avoid extra phase
disturbance when switching over to another main divider ratio as is
explained in the Serial Programming Input chapter.
At the completion of a main divider cycle, a main divider output
pulse is generated which will drive the main phase comparator.
Also, the fractional accumulator is incremented with NF. The
accumulator works modulo Q. Q is preset by the serial control bit
FMOD to 8 when FMOD = ‘0’. Each time the accumulator
overflows, the total divide ratio will be NMAIN + 1 for the next cycle.
The mean division ratio over Q main divider cycles will then be:
NQ
+ NMAIN ) NF
Q
Synchronization is provided to avoid a random phase on the phase
detector upon the loading of a new ratio and when powering up the
loop.
Auxiliary Divider
The input signal on INA is amplified to logic level by a single-ended
input buffer, which accepts low level AC-coupled input signals. This
input stage is enabled if the serial control bit PD2 = ‘1’. Disabling
means that all currents in the buffer and prescaler are switched off.
The auxiliary divider is programmed with 14 bits and has continuous
integer division ratios over the range of 128 to 16,384.
Reference Divider (Figure 8)
The input can be driven by a differential crystal input or an external
TCXO. This input stage is enabled by the OR function of the serial
input bits PD1 and PD2. Disabling means that all currents are
switched off. The reference divider consists of a programmable
divide by NREF (NREF = 4 to 1,023) followed by a 3-bit binary
counter. The 2 bit SM determines which of the four output pulses is
selected as the main phase detector signal. To obtain the best time
spacing for the main and auxiliary reference signals, a different
output will be used for the auxiliary phase detector, reducing the
possibility of unwanted interactions.




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