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ST16C1450IQ48 Fiches technique(PDF) 6 Page - Exar Corporation

No de pièce ST16C1450IQ48
Description  2.97V TO 5.5V UART
Download  28 Pages
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Fabricant  EXAR [Exar Corporation]
Site Internet  http://www.exar.com
Logo EXAR - Exar Corporation

ST16C1450IQ48 Fiches technique(HTML) 6 Page - Exar Corporation

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ST16C1450
xr
2.97V TO 5.5V UART
REV. 4.2.1
6
2.4
Transmitter
The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and an 8-bit Transmit Holding
Register (THR). TSR shifts out every data bit with the 16X internal clock. A bit time is 16 clock periods. The
transmitter sends the start-bit followed by the number of data bits, inserts the proper parity-bit if enabled, and
adds the stop-bit(s). The status of the THR and TSR are reported in the Line Status Register (LSR bit-5 and bit-
6).
2.4.1
Transmit Holding Register (THR) - Write Only
The transmit holding register is an 8-bit register providing a data interface to the host processor. The host
writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,
parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out.
2.4.2
Transmitter Operation
The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the
data byte is transferred to TSR. The THR flag can generate a transmit empty interrupt (ISR bit-1) when it is
enabled by IER bit-1. The TSR flag (LSR bit-6) is set when both the THR and TSR become completely empty.
TABLE 1: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK
OUTPUT Data Rate
DIVISOR FOR 16x
Clock (Decimal)
DIVISOR FOR 16x
Clock (HEX)
DLM PROGRAM
VALUE (HEX)
DLL PROGRAM
VALUE (HEX)
DATA RATE
ERROR (%)
400
2304
900
09
00
0
2400
384
180
01
80
0
4800
192
C0
00
C0
0
9600
96
60
00
60
0
19.2k
48
30
00
30
0
38.4k
24
18
00
18
0
76.8k
12
0C
00
0C
0
153.6k
6
06
00
06
0
230.4k
4
04
00
04
0
460.8k
2
02
00
02
0
921.6k
1
01
00
01
0


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