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ST16C1450IQ48 Fiches technique(PDF) 3 Page - Exar Corporation

No de pièce ST16C1450IQ48
Description  2.97V TO 5.5V UART
Download  28 Pages
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Fabricant  EXAR [Exar Corporation]
Site Internet  http://www.exar.com
Logo EXAR - Exar Corporation

ST16C1450IQ48 Fiches technique(HTML) 3 Page - Exar Corporation

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ST16C1450
REV. 4.2.1
2.97V TO 5.5V UART
3
PIN DESCRIPTIONS
NAME
28-PIN
PLCC
48-PIN
TQFP
TYPE
DESCRIPTION
DATA BUS INTERFACE
A0
A1
A2
21
20
19
30
28
27
I
Address data lines [2:0]. A2:A0 selects internal UART’s configuration registers.
D0
D1
D2
D3
D4
D5
D6
D7
1
2
3
4
5
6
7
8
43
45
46
47
3
4
5
6
I/O
Data bus lines [7:0] (bidirectional).
IOR#
16
20
I
Input/Output Read (active low). The falling edge instigates an internal read cycle and
retrieves the data byte from an internal register pointed by the address lines [A2:A0],
places it on the data bus to allow the host processor to read it on the leading edge.
IOW#
14
17
I
Input/Output Write (active low). The falling edge instigates the internal write cycle and
the rising edge transfers the data byte on the data bus to an internal register pointed by
the address lines [A2:A0].
CS#
11
9
I
Chip Select input (active low). A logic 0 on this pin selects the ST16C1450 device.
INT
18
23
O
Interrupt Output (three-state, active high). INT output defaults to three-state mode and
becomes active high when MCR bit-3 is set to a logic 1. INT output becomes a logic
high level when interrupts are enabled in the interrupt enable register (IER), and
whenever the transmitter, receiver, line and/or modem status register has an active
condition.
MODEM OR SERIAL I/O INTERFACE
TX
10
8
O
Transmit Data. This output is associated with individual serial transmit channel data
from the 1450. The TX signal will be a logic 1 during reset, idle (no data), or when the
transmitter is disabled. During the local loopback mode, the TX output pin is disabled
and TX data is internally connected to the UART RX input.
RX
9
7
I
Receive Data. This input is associated with individual serial channel data to the 1450.
Normal received data input idles at logic 1 condition. This input must be connected to
its idle logic state, logic 1, else the receiver may report “receive break” and/or “error”
condition(s).
RTS#
22
31
O
Request to Send or general purpose output (active low). If this pin is not needed for
modem communication, then it can be used as a general I/O. If it is not used, leave it
unconnected.
CTS#
25
34
I
Clear to Send or general purpose input (active low). If this pin is not needed for modem
communication, then it can be used as a general I/O. If it is not used, connect it to
VCC.
DTR#
23
32
O
Data Terminal Ready or general purpose output (active low). If this pin is not needed
for modem communication, then it can be used as a general I/O. If it is not used, leave
it unconnected.


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