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KMPC885ZP80 Fiches technique(PDF) 2 Page - Freescale Semiconductor, Inc |
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KMPC885ZP80 Fiches technique(HTML) 2 Page - Freescale Semiconductor, Inc |
2 / 92 page MPC885/MPC880 Hardware Specifications, Rev. 3 2 Freescale Semiconductor Features Table 1 shows the functionality supported by the members of the MPC885 family. 2Features The MPC885/880 is comprised of three modules that each use the 32-bit internal bus: a MPC8xx core, a system integration unit (SIU), and a communications processor module (CPM). The following list summarizes the key MPC885/880 features: • Embedded MPC8xx core up to 133 MHz • Maximum frequency operation of the external bus is 80 MHz (in 1:1 mode) — The 133-MHz core frequency supports 2:1 mode only. — The 66-/80-MHz core frequencies support both the 1:1 and 2:1 modes. • Single-issue, 32-bit core (compatible with the PowerPC architecture definition) with thirty-two 32-bit general-purpose registers (GPRs) — The core performs branch prediction with conditional prefetch and without conditional execution. — 8-Kbyte data cache and 8-Kbyte instruction cache (see Table 1) – Instruction cache is two-way, set-associative with 256 sets in 2 blocks – Data cache is two-way, set-associative with 256 sets – Cache coherency for both instruction and data caches is maintained on 128-bit (4-word) cache blocks. – Caches are physically addressed, implement a least recently used (LRU) replacement algorithm, and are lockable on a cache block basis. — MMUs with 32-entry TLB, fully associative instruction and data TLBs — MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16 virtual address spaces and 16 protection groups — Advanced on-chip emulation debug mode • Provides enhanced ATM functionality found on the MPC862 and MPC866 families and includes the following: — Improved operation, administration and maintenance (OAM) support — OAM performance monitoring (PM) support — Multiple APC priority levels available to support a range of traffic pace requirements — Port-to-port switching capability without the need for RAM-based microcode — Simultaneous MII (100BaseT) and UTOPIA (half- or full -duplex) capability — Optional statistical cell counters per PHY Table 1. MPC885 Family Part Cache Ethernet SCC SMC USB ATM Support Security Engine I Cache D Cache 10BaseT 10/100 MPC885 8 Kbyte 8 Kbyte Up to 3 2 3 2 1 Serial ATM and UTOPIA interface Yes MPC880 8 Kbyte 8 Kbyte Up to 2 2 2 2 1 Serial ATM and UTOPIA interface No |
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Description similaire - KMPC885ZP80 |
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