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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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TMP470R1B512PGE Fiches technique(PDF) 9 Page - Analog Devices |
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TMP470R1B512PGE Fiches technique(HTML) 9 Page - Analog Devices |
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9 / 49 page  www.ti.com TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A – SEPTEMBER 2005 – REVISED AUGUST 2006 Table 2. Terminal Functions (continued) TERMINAL INTERNAL TYPE(1)(2) PULLUP/ DESCRIPTION NAME NO. PULLDOWN(3) MULTI-BUFFERED ANALOG-TO-DIGITAL CONVERTER (MibADC) (CONTINUED) ADIN[13] 112 ADIN[14] 110 3.3-V I MibADC analog input pins ADIN[15] 103 ADREFHI 116 3.3-V REF I MibADC module high-voltage reference input ADREFLO 117 GND REF I MibADC module low-voltage reference input VCCAD 118 3.3-V PWR MibADC analog supply voltage VSSAD 119 GND MibADC analog ground reference SERIAL PERIPHERAL INTERFACE 1 (SPI1) SPI1CLK 5 SPI1 clock. SPI1CLK can be programmed as a GIO pin. SPI1ENA 1 SPI1 chip enable. SPI1ENA can be programmed as a GIO pin. SPI1SCS 2 SPI1 slave chip select. SPI1SCS can be programmed as a GIO pin. 3.3-V I/O IPD (20 µA) SPI1 data stream. Slave in/master out. SPI1SIMO can be programmed as SPI1SIMO 3 a GIO pin. SPI1 data stream. Slave out/master in. SPI1SOMI can be programmed as SPI1SOMI 4 a GIO pin. SERIAL PERIPHERAL INTERFACE 2 (SPI2) SPI2CLK 62 SPI2 clock. SPI2CLK can be programmed as a GIO pin. SPI2ENA 65 SPI2 chip enable. SPI2ENA can be programmed as a GIO pin. SPI2SCS 66 SPI2 slave chip select. SPI2SCS can be programmed as a GIO pin. 3.3-V I/O IPD (20 µA) SPI2 data stream. Slave in/master out. SPI2SIMO can be programmed as SPI2SIMO 63 a GIO pin. SPI2 data stream. Slave out/master in. SPI2SOMI can be programmed as SPI2SOMI 64 a GIO pin. SERIAL PERIPHERAL INTERFACE 3 (SPI3) SPI3CLK 94 SPI3 clock. SPI3CLK can be programmed as a GIO pin. SPI3ENA 98 SPI3 chip enable. SPI3ENA can be programmed as a GIO pin. SPI3SCS 97 SPI3 slave chip select. SPI3SCS can be programmed as a GIO pin. 3.3-V I/O IPD (20 µA) SPI3 data stream. Slave in/master out. SPI3SIMO can be programmed as SPI3SIMO 96 a GIO pin. SPI3 data stream. Slave out/master in. SPI3SOMI can be programmed as SPI3SOMI 95 a GIO pin. ZERO-PIN PHASE-LOCKED LOOP (ZPLL) OSCIN 13 1.8-V I Crystal connection pin or external clock input OSCOUT 12 1.8-V O External crystal connection pin Enable/disable the ZPLL. The ZPLL can be bypassed and the oscillator becomes the system clock. If not in bypass mode, TI recommends that this PLLDIS 73 3.3-V I IPD (20 µA) pin be connected to ground or pulled down to ground by an external resistor. SERIAL COMMUNICATIONS INTERFACE 1 (SCI1) SCI1CLK 89 3.3-V I/O IPD (20 µA) SCI1 clock. SCI1CLK can be programmed as a GIO pin. SCI1RX 91 3.3-V I/O IPU (20 µA) SCI1 data receive. SCI1RX can be programmed as a GIO pin. SCI1TX 90 3.3-V I/O IPU (20 µA) SCI1 data transmit. SCI1TX can be programmed as a GIO pin. SERIAL COMMUNICATIONS INTERFACE 2 (SCI2) SCI2CLK 45 3.3-V I/O IPD (20 µA) SCI2 clock. SCI2CLK can be programmed as a GIO pin. SCI2RX 43 3.3-V I/O IPU (20 µA) SCI2 data receive. SCI2RX can be programmed as a GIO pin. SCI2TX 44 3.3-V I/O IPU (20 µA) SCI2 data transmit. SCI2TX can be programmed as a GIO pin. 9 Submit Documentation Feedback |
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