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ADM1185ARMZ-1 Fiches technique(PDF) 10 Page - Analog Devices

No de pièce ADM1185ARMZ-1
Description  Quad Voltage Monitor and Sequencer
Download  16 Pages
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Site Internet  http://www.analog.com
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ADM1185ARMZ-1 Fiches technique(HTML) 10 Page - Analog Devices

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ADM1185
Rev. 0 | Page 10 of 16
VOLTAGE MONITORING AFTER POWER-ON
Once PWRGD is asserted, the logical core latches into a different
mode of operation. During the initial power-up phase, each
output directly depends on an input (for example, VIN3 asserting
causes OUT3 to assert). When power-up is complete, this
function is redundant.
Once in the PWRGD state, the following behavior can be observed:
If the main 3.3 V supply monitored via VIN1 faults in the
power-good state, the PWRGD output is deasserted to
warn the downstream controller. All outputs (OUT1 to
OUT3) are immediately turned off, disabling all locally
generated supplies.
If a supply monitored by VIN2 to VIN4 fails, the PWRGD
output is deasserted to warn the controller, but the other
outputs are not deasserted.
Figure 20 and Figure 21 are waveforms that highlight the
behavior of the ADM1185 under various fault situations during
normal operation (that is, in the mode of operation after
PWRGD is asserted).
STATE1
START
VIN1 = OK
(DELAY = 190ms TYP)
STATE2
OUT1
ON
VIN2 = OK
STATE3
OUT1, OUT2
ON
VIN3 = OK
STATE4
OUT1, OUT2, OUT3
ON
VIN4 = OK
(DELAY = 100ms MIN)
STATE5
PWRGD
VIN2. VIN3. VIN4 = FAULT
VIN1 = FAULT
VIN1 = FAULT
VIN1 = FAULT
VIN1 = FAULT
Figure 19. Flow Diagram Highlighting the Different Modes of Operation
of the Logical Core


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