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AD9516-2 Fiches technique(PDF) 4 Page - Analog Devices

No de pièce AD9516-2
Description  14-Output Clock Generator with Integrated 2.2 GHz VCO
Download  84 Pages
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
Logo AD - Analog Devices

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AD9516-2
Rev. 0 | Page 4 of 84
SPECIFICATIONS
Typical (typ) is given for VS = VS_LVPECL = 3.3 V ± 5%; VS ≤ VCP ≤ 5.25 V; TA = 25°C; RSET = 4.12 kΩ; CPRSET = 5.1 kΩ,
unless otherwise noted. Minimum (min) and maximum (max) values are given over full VS and TA (−40°C to +85°C) variation.
POWER SUPPLY REQUIREMENTS
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
VS
3.135
3.3
3.465
V
This is 3.3 V ± 5%
VS_LVPECL
2.375
VS
V
This is nominally 2.5 V to 3.3 V ± 5%
VCP
VS
5.25
V
This is nominally 3.3 V to 5.0 V ± 5%
RSET Pin Resistor
4.12
Sets internal biasing currents; connect to ground
CPRSET Pin Resistor
5.1
Sets internal CP current range, nominally 4.8 mA (CP_lsb = 600 μA);
actual current can be calculated by: CP_lsb = 3.06/CPRSET; connect to ground
BYPASS Pin Capacitor
220
nF
Bypass for internal LDO regulator; necessary for LDO stability; connect to ground
PLL CHARACTERISTICS
Table 2.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
VCO (ON-CHIP)
Frequency Range
2050
2335
MHz
See Figure 15
VCO Gain (KVCO)
50
MHz/V
See Figure 10
Tuning Voltage (VT)
0.5
VCP − 0.5
V
VCP ≤ VS when using internal VCO; outside of this
range, the CP spurs may increase due to CP up/
down mismatch
Frequency Pushing (Open-Loop)
1
MHz/V
Phase Noise @ 100 kHz Offset
−107
dBc/Hz
f = 2175 MHz
Phase Noise @ 1 MHz Offset
−124
dBc/Hz
f = 2175 MHz
REFERENCE INPUTS
Differential Mode (REFIN, REFIN)
Differential mode (can accommodate single-
ended input by ac grounding undriven input)
Input Frequency
0
250
MHz
Frequencies below about 1 MHz should be
dc-coupled; be careful to match VCM (self-bias voltage)
Input Sensitivity
250
mV p-p
PLL figure of merit increases with increasing
slew rate; see Figure 14
Self-Bias Voltage, REFIN
1.35
1.60
1.75
V
Self-bias voltage of REFIN1
Self-Bias Voltage, REFIN
1.30
1.50
1.60
V
Self-bias voltage of REFIN1
Input Resistance, REFIN
4.0
4.8
5.9
Self-biased1
Input Resistance, REFIN
4.4
5.3
6.4
Self-biased1
Dual Single-Ended Mode (REF1, REF2)
Two single-ended CMOS-compatible inputs
Input Frequency (AC-Coupled)
20
250
MHz
Slew rate > 50 V/μs
Input Frequency (DC-Coupled)
0
250
MHz
Slew rate > 50 V/μs; CMOS levels
Input Sensitivity (AC-Coupled)
0.8
V p-p
Should not exceed VS p-p
Input Logic High
2.0
V
Input Logic Low
0.8
V
Input Current
−100
+100
μA
Input Capacitance
2
pF
Each pin, REFIN/REFIN (REF1/REF2)


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