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AD8153 Fiches technique(PDF) 4 Page - Analog Devices |
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AD8153 Fiches technique(HTML) 4 Page - Analog Devices |
4 / 24 page AD8153 Rev. 0 | Page 4 of 24 I2C TIMING SPECIFICATIONS SDA SCL tf tLOW tHD;STA tr tHD;DAT tHIGH tSU;DAT tf tSU;STA tHD;STA tSP tSU;STO tr tBUF S P Sr S Figure 2. I2C Timing Diagram Table 2. Parameter Symbol Min Max Unit SCL Clock Frequency fSCL 0 400+ kHz Hold Time for a Start Condition tHD;STA 0.6 – μs Set-up Time for a Repeated Start Condition tSU;STA 0.6 – μs Low Period of the SCL Clock tLOW 1.3 – μs High Period of the SCL Clock tHIGH 0.6 – μs Data Hold Time tHD;DAT 0 – μs Data Set-Up Time tSU;DAT 10 – ns Rise Time for Both SDA and SCL tr 1 300 ns Fall Time for Both SDA and SCL tf 1 300 ns Set-Up Time for Stop Condition tSU;STO 0.6 – μs Bus Free Time Between a Stop Condition and a Start Condition tBUF 1 – ns Capacitance for Each I/O Pin Ci 5 7 pF |
Numéro de pièce similaire - AD8153_07 |
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Description similaire - AD8153_07 |
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