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AD1987JCPZ Fiches technique(PDF) 10 Page - Analog Devices |
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AD1987JCPZ Fiches technique(HTML) 10 Page - Analog Devices |
10 / 18 page Rev. 0 | Page 10 of 18 | May 2007 AD1987 Table 5. AD1987 Pin Descriptions Mnemonic Pin No. Function Description DIGITAL INTERFACE SDATA_OUT BIT_CLK SDATA_IN SYNC RESET 5 6 8 10 11 I I I/O I I Link Serial Data Output. Clocked on both edges of BIT_CLK. Link Bit Clock. 24.000 MHz serial data clock. Link Serial Data Input. AD1987 output stream clocked only on one edge of BIT_CLK. Link Frame Sync. Link Reset. Master hardware reset. DIGITAL I/O GPIO_0 GPIO_1/EAPD S/PDIF_OUT 2 47 48 I/O I/O O General Purpose Input/Output Pin. Digital signal used to control external circuitry. General Purpose Input/Output Pin/EAPD Pin. Digital signal used to control external circuitry. By default pin is in a Hi-Z state. When used as EAPD: Hi-Z = amp-on, DVSS = amp off. S/PDIF_OUT. Supports S/PDIF output. JACK SENSE SENSE_A/SRC_B SENSE_B/SRC_A 13 34 I/O I/O JACK Sense A-D Input/Sense B drive. JACK Sense E-H Input/Sense A drive. ANALOG I/O PCBEEP Port E_L Port E_R Port F_L Port F_R CD_L CD_GND CD_R Port B_L Port B_R Port C_L Port C_R Port D_L Port D_R Port A_L MONO_OUT Port A_R Port G_L Port G_R Port H_L Port H_R 2 14 15 16 17 18 19 20 21 22 23 24 35 36 39 40 41 43 44 45 46 LI LI, MIC, LO, SWAP LI, MIC, LO, SWAP LO LO LI LI LI LI, MIC, HP, LO LI, MIC, HP, LO LI, MIC, LO LI, MIC, LO LI, HP, LO LI, HP, LO LI, MIC, HP, LO LO LI, MIC, HP, LO LO, SWAP LO, SWAP LO LO Monaural Input From System for Analog PCBeep. Auxiliary Input/Output Left Channel. Auxiliary Input/Output Right Channel. Auxiliary Input/Output Left Channel. Auxiliary Input/Output Right Channel. CD Audio Left Channel. CD-Audio-Analog-Ground-Reference (for Differential CD Input). Must be connected to AGND via 0.1 μF capacitor if not in use as CD_GND. CD Audio Right Channel. Front Panel Stereo MIC/Line-In. Front Panel Stereo MIC/Line-In. Rear Panel Stereo MIC/Line-In. Rear Panel Stereo MIC/Line-In. Rear Panel Headphone/Line-Out. Rear Panel Headphone/Line-Out. Front Panel Headphone/Line-Out. Monaural Output to Internal Speaker or Telephony Subsystem Speakerphone. Front Panel Headphone/Line-Out. Rear Panel C/LFE Output. Rear Panel C/LFE Output. Rear Panel Surround Center/Side. Rear Panel Surround Center/Side. FILTER/REFERENCE MIC_BIAS-B MIC_BIAS-C MIC_BIAS-E V REF_FILT MIC_BIAS-A DVCORE 28 29 31 33 37 1 O O O O O O Switchable Microphone Bias. For use with Port B (Pins 21, 22). Switchable Microphone Bias. For use with Port C (Pins 23, 24). Switchable Microphone Bias. For use with Port E (Pins 14, 15). Voltage Reference Filter. Switchable Microphone Bias. For use with Port A (Pins 39, 41) All MIC_BIAS pins are capable of: Hi-Z, 0 V, 1.65 V, 3.78 V, and 3.95 V (with 5.0 V on Pin 33) Hi-Z, 0 V, 1.65 V, 2.86 V, and 3.00 V (with 3.3 V on Pin 33). CAUTION: DO NOT APPLY 3.3 V TO THIS PIN! Filter connection for internal core voltage regulator. This pin must be connected to filter caps: 10 μF, 1.0 μF and 0.1 μF connected in parallel between Pin 1 and DVSS (Pin 4). The symbols used in this table are defined as: I = Input, O = Output, LI = Line level input, LO = Line level output, HP = Output capable of driving headphone load, MIC = Input supports microphones with MIC bias and boost amplifier, SWAP = Outputs can swap L/R channels (typically used to support C/LFE or shared C/LFE function). |
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Description similaire - AD1987JCPZ |
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