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SN65LVDS303

SLLS743A – JULY 2006 – REVISED JANUARY 2007

Table 2. TERMINAL FUNCTIONS

NAME

I/O

DESCRIPTION

D0+, D0–

SubLVDS data link (active during normal operation)

SubLVDS data link (active during normal operation when LS = high; high impedance if

D1+, D1–

SubLVDS out

LS = low)

CLK+, CLK–

SubLVDS output clock; clock polarity is fixed.

R0–R7

Red pixel data (8); terminal assignment depends on SWAP terminal setting.

G0–G7

Green pixel data (8); terminal assignment depends on SWAP terminal setting.

B0–B7

Blue pixel data (8); terminal assignment depends on SWAP terminal setting.

HS

Horizontal sync

VS

Vertical sync

DE

Data enable

PCLK

Input pixel clock; rising or falling clock polarity is selected by control input CPOL.

CMOS in

LS

Link select (determines active SubLVDS data links and PLL range); see Table 3.

Disables the CMOS drivers and turns off the PLL, putting device in shutdown mode

1 – Transmitter enabled

0 – Transmitter disabled (shutdown)

Note: The TXEN input incorporates glitch-suppression logic to avoid device malfunction

TXEN

on short input spikes. It is necessary to pull TXEN high for longer than 10

µs to enable

the transmitter. It is necessary to pull the TXEN input low for longer than 10

µs to

disable the transmitter. At power up, the transmitter is enabled immediately if TXEN = 1

and disabled if TXEN = 0

Input clock polarity selection

CPOL

CMOS in

0 – rising edge clocking

1 – falling edge clocking

Bus swap. Swaps the bus terminals to allow device placement on top or bottom of PCB.

See pinout drawing for terminal assignments.

SWAP

CMOS in

0 – data input from B0...R7

1 – data input from R7...B0

Supply voltage

GND

Supply ground

SubLVDS I/O supply voltage

SubLVDS ground

PLL analog supply voltage

PLL analog GND

PLL digital supply voltage

PLL digital GND

(1)

For a multilayer PCB, it is recommended to keep one common GND layer underneath the device and connect all ground terminals

directly to this plane.

6

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