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FMS6406_06 Datasheet(Fiches technique) 1 Page - Fairchild Semiconductor

Numéro de pièce FMS6406_06
Description  Precision S-Video Filter with Summed Composite Output, Sound Trap, and Group Delay Compensation
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Fabricant  FAIRCHILD [Fairchild Semiconductor]
Site Internet  http://www.fairchildsemi.com
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© 2006 Fairchild Semiconductor Corporation

www.fairchildsemi.com
FMS6406 Rev. 4.0.4
August 2006
FMS6406
Precision S-Video Filter with Summed Composite
Output, Sound Trap, and Group Delay Compensation
Features
7.6MHz 5th-order Y,C filters with composite summer
14dB notch at 4.425MHz to 4.6MHz for sound trap
capable of handling stereo
50dB stopband attenuation at 27MHz on Y, C,
and CV outputs
Better than 0.5dB flatness to 4.2MHz on Y, C,
and CV outputs
Equalizer and notch filter for driving RF modulator with
group delay of -180ns
No external frequency selection components or clocks
< 5ns group delay on Y, C, and CV outputs
AC coupled inputs
AC or DC coupled outputs
Capable of PAL frequency for Y, C, CV
Continuous Time Low Pass Filters
<1.4% differential gain with 0.7° differential phase
on Y, C, and CV channels
Integrated DC restore circuitry with low tilt
Applications
Cable set-top boxes
Satellite set-top boxes
DVD players
Description
The FMS6406 is a dual Y/C 5th-order Butterworth lowpass
video filter optimized for minimum overshoot and flat
group delay. The device also contains a summing circuit
to generate filtered composite video, an audio trap and
group delay compensation circuit. The audio trap removes
video information in the spectral location of the subsequent
RF audio carrier. The group delay circuit predistorts the
signal to compensate for the inherent receiver IF filter’s
group delay distortion.
In a typical application, the Y and C input signals from
DACs are AC-coupled into the filters. Both channels have
DC-restore circuitry to clamp the DC-input levels during
video sync. The Y and C channels use separate feedback
clamps. The clamp pulse is derived from the Y channel.
All outputs are capable of driving 2Vpp, AC or DC-coupled,
into either a single or dual video load. A single video load
consists of a series 75
W impedance matching resistor
connected to a terminated 75
W line, this presents a total
of 150
W of loading to the part. A dual load would be two of
these in parallel which would present a total of 75
W to the
part. The gain of the Y, C and CV signals is 6dB with 1Vpp
input levels. All video channels are clamped during sync
to establish the appropriate output voltage reference levels.
Ordering Information
Part Number
Package
Pb-Free
Operating Temp
Range
Packaging
Method
FMS6406CS
SOIC-8
Yes
0°C to +70°C
Tube
FMS6406CSX
SOIC-8
Yes
0°C to +70°C
Tape and Reel
Block Diagram
YIN
CIN
COUT
EQ_NOTCH
YOUT
Sync Strip
Reference
and Timing
CVOUT
gM
250mV
gM
250mV
6dB
8
2
5
3
7
1
4
GND
VCC
6dB
6
Σ
+
+
Notch
Group
Delay




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