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ISL6128IR Fiches technique(PDF) 8 Page - Intersil Corporation |
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ISL6128IR Fiches technique(HTML) 8 Page - Intersil Corporation |
8 / 21 page 8 FN9005.8 February 5, 2007 Figure 2 illustrates the turn-on and Figure 3 illustrates the nominal turnoff timing diagram of the ISL6123 and ISL6124 product. The ISL6125 is similar to the ISL6124 except that instead of charge pumped GATE outputs, there are sequenced open drain outputs that can be pulled up to a maximum of VDD. Note the delay and flexible sequencing possibilities. Multiple series, parallel or adjustable capacitors can be used to easily fine tune timing between that offered by standard value capacitors. l TABLE 1. NOMINAL DELAY TO SEQUENCING THRESHOLD DLY PIN CAPACITANCE TIME(s) Open 0.00006 100pF 0.00013 1000pF 0.0013 0.01 μF 0.013 0.1 μF0.13 1 μF1.3 10 μF13 NOTE: Nom. TDEL_SEQ = Cap (μF) * 1.3MΩ. FIGURE 2. ISL6123, ISL6124 TURN-ON AND GLITCH RESPONSE TIMING DIAGRAM UVLO_B UVLO_C UVLO_D ENABLE (ISL6123) RESET# DLYON_A DLYON_B DLYON_C DLYON_D GATE_A GATE_B GATE_C GATE_D UVLO_A VEN DLY_Vth DLY_Vth DLY_Vth DLY_Vth VQPUMP VQPUMP VQPUMP ENABLE# (ISL6124) VUVLOVth VUVLOVth VUVLOVth VUVLOVth TRSTdel TUVLOdel VQPUMP-1V VQPUMP <TFIL ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130 |
Numéro de pièce similaire - ISL6128IR |
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Description similaire - ISL6128IR |
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