5

FN6410.0

December 18, 2006

Full

-2

1.1

2

μA

Full

-

4

-

M

Ω

NOTES:

5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.

6. Parameters with limits are 100% tested at +25°C. Limits across the full temperature range are guaranteed by design and correlation.

7. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range.

Test Circuits and Waveforms

Logic input waveform is inverted for switches that have the opposite

logic sense.

FIGURE 1A. MEASUREMENT POINTS

capacitance.

FIGURE 1B. TEST CIRCUIT

FIGURE 1. SWITCHING TIMES

FIGURE 2A. MEASUREMENT POINTS

capacitance.

FIGURE 2B. TEST CIRCUIT

FIGURE 2. BREAK-BEFORE-MAKE TIME

PARAMETER

TEST CONDITIONS

TEMP

(°C)

(NOTE 5)

MIN

TYP

(NOTE 5)

MAX

UNITS

50%

90%

0V

0V

LOGIC

INPUT

SWITCH

INPUT

SWITCH

OUTPUT

90%

V

OUT

V

(INPUT)

R

L

R

L

R

ON

()

+

------------------------------

=

SWITCH

INPUT

COMx

NO or NC

IN

50

Ω

10pF

GND

C

CTRL

90%

0V

LOGIC

INPUT

SWITCH

OUTPUT

0V

IN

COMx

10pF

50

Ω

NOx

NCx

GND

C

CTRL

ISL54208