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74LVQ138 Fiches technique(PDF) 1 Page - Fairchild Semiconductor |
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74LVQ138 Fiches technique(HTML) 1 Page - Fairchild Semiconductor |
1 / 6 page © 2001 Fairchild Semiconductor Corporation DS011350 www.fairchildsemi.com February 1992 Revised June 2001 74LVQ138 Low Voltage 1-of-8 Decoder/Demultiplexer General Description The LVQ138 is a high-speed 1-of-8 decoder/demultiplexer. This device is ideally suited for high-speed bipolar memory chip select address decoding. The multiple input enables allow parallel expansion to a 1-of-24 decoder using just three LVQ138 devices or a 1-of-32 decoder using four LVQ138 devices and one inverter. Features s Ideal for low power/low noise 3.3V applications s Guaranteed simultaneous switching noise level and dynamic threshold performance s Improved latch-up immunity s Guaranteed incident wave switching into 75 Ω s 4kV minimum ESD immunity s Demultiplexing capability s Multiple input enable for each expansion s Active LOW mutually exclusive outputs Ordering Code: Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols IEEE/IEC Connection Diagram Pin Descriptions Order Number Package Number Package Description 74LVQ138SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74LVQ138SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Pin Names Description A0–A2 Address Inputs E1–E2 Enable Inputs E3 Enable Input O0–O7 Outputs |
Numéro de pièce similaire - 74LVQ138 |
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Description similaire - 74LVQ138 |
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