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AM49LV128BMH15NS Fiches technique(PDF) 9 Page - SPANSION

No de pièce AM49LV128BMH15NS
Description  128 Megabit (8 M x 16-Bit) MirrorBit??Uniform Sector Flash Memory and 32 Mbit (2 M x 16-Bit)
Download  98 Pages
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AM49LV128BMH15NS Fiches technique(HTML) 9 Page - SPANSION

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June 17, 2004
Am49LV128BM
7
LOOK AHEAD PINOUT
In order to provide customers with a migration path to
higher densities, as well as the option to stack more
die in a package, FASL has prepared a standard pi-
nout that supports:
NOR Flash and SRAM densities up to 4 Gigabits
NOR Flash and pSRAM densities up to 4 Gigabits
NOR Flash and pSRAM and DATA STORAGE densities up
to 4 Gigabits.
The signal locations of the resultant MCP device are
shown above. Note that for different densities, the ac-
tual package outline may vary. However, any pinout in
any MCP will be a subset of the pinout above.
In some cases, there may be outrigger balls in loca-
tions outside the grid shown above. In such cases, the
user is recommended to treat these as RFU’s, and not
connect them to any other signal.
In case of any further inquiries about the above look-
ahead pinout, please refer to the application note on
this subject, or contact the appropriate AMD or Fujitsu
sales office.
D2
E2
F2
G2
H2
J2
C3
D3
E3
F3
G3
H3
J3
K3
C4
D4
E4
F4
G4
H4
J4
K4
C5
D5
E5
H5
J5
K5
C6
D6
E6
H6
J6
K6
C7
D7
E7
F7
G7
H7
J7
K7
C8
D8
E8
F8
G8
H8
J8
K8
D9
E9
F9
G9
H9
J9
WP#
A3
A2
A0
CE#f1
CE#1ps
VSSds
A7
A6
A5
VSS
OE#
DQ0
DQ8
CLK
LB#
UB#s
A18
DQ1
DQ9
DQ10
DQ2
CE#f2
WP/ACC
RST#f
DQ3
VCCf
DQ11
VCCds
WE#
CE2s1
DQ4
VCCps
NC
RST#ds
A8
A19
A9
DQ6
DQ13
DQ12
DQ5
CLK#ds
A11
A12
A14
NC
DQ15
DQ7
DQ14
CE#1ds
A15
A22
A16
NC
VSS
Pseudo
SRAM Only
Shared
Flash Only
K2
CE#1ps
K9
CE#1ps
L3
L4
L5
L6
L7
L8
DQ8
DQ2
DQ11
NC
DQ5
DQ14
L2
CE#1ps
L9
CE#1ps
M3
M4
M5
M6
M7
M8
DQ8
DQ2
DQ11
NC
DQ5
DQ14
M2
CE#1ps
M9
CE#1ps
N1
P1
NC
NC
N2
NC
P2
NC
N9
P9
NC
NC
N10
NC
P10
NC
F5
G5
F6
G6
RY/BY#
VCCf
A20
VCCps
C9
RY/BY#ds
C2
ADV#
A9
B9
NC
NC
A10
NC
B10
NC
A1
B1
NC
NC
A2
NC
B2
NC


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