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AM50DL9608GT70IT Fiches technique(PDF) 9 Page - SPANSION |
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AM50DL9608GT70IT Fiches technique(HTML) 9 Page - SPANSION |
9 / 70 page 8 Am50DL9608G May 19, 2003 P R E L I M I NARY PIN DESCRIPTION A18–A0 = 19 Address Inputs (Common) A21–A19, A-1 = 4 Address Inputs (Flash) DQ15–DQ0 = 16 Data Inputs/Outputs (Common) CE#f1 = Flash Chip Enable 1 (Am29DL640G) CE#f2 = Flash Chip Enable 2 (Am29DL320G) CE#1s = Pseudo SRAM Chip Enable 1 CE2s = Pseudo SRAM Chip Enable 2 OE# = Output Enable (Common) WE# = Write Enable (Common) RY/BY# = Ready/Busy Output UB#s = Upper Byte Control (Pseudo SRAM) LB#s = Lower Byte Control (Pseudo SRAM) RESET# = Hardware Reset Pin, Active Low WP#/ACC = Hardware Write Protect/ Acceleration Pin (Flash) V CCf = Flash 3.0 volt-only single power sup- ply (see Product Selector Guide for speed options and voltage supply tolerances) V CCs = Pseudo SRAM Power Supply V SS = Device Ground (Common) NC = Pin Not Connected Internally LOGIC SYMBOL 19 16 DQ15–DQ0 A18–A0 CE#f1 OE# WE# RESET# UB#s RY/BY# WP#/ACC A21–A19 LB#s CE1#s CE2s CE#f2 |
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