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AD9949KCP Fiches technique(PDF) 1 Page - Analog Devices |
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AD9949KCP Fiches technique(HTML) 1 Page - Analog Devices |
1 / 36 page 12-Bit CCD Signal Processor with Precision Timing Core AD9949 Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. FEATURES New AD9949A supports CCD line length > 4096 pixels Correlated double sampler (CDS) 0 dB to 18 dB pixel gain amplifier (PxGA®) 6 dB to 42 dB 10-bit variable gain amplifier (VGA) 12-bit, 36 MSPS analog-to-digital converter (ADC) Black level clamp with variable level control Complete on-chip timing driver Precision Timing™ core with < 600 ps resolution On-chip 3 V horizontal and RG drivers 40-lead LFCSP package APPLICATIONS Digital still cameras High speed digital imaging applications GENERAL DESCRIPTION The AD9949 is a highly integrated CCD signal processor for digital still camera applications. Specified at pixel rates of up to 36 MHz, the AD9949 consists of a complete analog front end with A/D conversion, combined with a programmable timing driver. The Precision Timing core allows adjustment of high speed clocks with < 600 ps resolution. The analog front end includes black level clamping, CDS, PxGA, VGA, and a 36 MSPS, 12-bit ADC. The timing driver provides the high speed CCD clock drivers for RG and H1 to H4. Operation is programmed using a 3-wire serial interface. Packaged in a space-saving, 40-lead LFCSP package, the AD9949 is specified over an operating temperature range of −20°C to +85°C. FUNCTIONAL BLOCK DIAGRAM CLAMP DOUT CCDIN REFT REFB INTERNAL REGISTERS 6dB TO 42dB SYNC GENERATOR SDATA SCK SL HBLK VGA AD9949 PRECISION TIMING CORE 12-BIT ADC VREF INTERNAL CLOCKS PxGA CDS HORIZONTAL DRIVERS RG H1 TO H4 HD VD CLI CLP/PBLK 0dB TO 18dB 4 12 Figure 1. |
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