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AM42DL6404G Fiches technique(PDF) 58 Page - Advanced Micro Devices

No de pièce AM42DL6404G
Description  64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 4 Mbit (256 K x 16-Bit) Static RAM
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Fabricant  AMD [Advanced Micro Devices]
Site Internet  http://www.amd.com
Logo AMD - Advanced Micro Devices

AM42DL6404G Fiches technique(HTML) 58 Page - Advanced Micro Devices

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March 20, 2002
Am42DL6404G
57
PR ELI M I NARY
FLASH ERASE AND PROGRAMMING PERFORMANCE
Notes:
1. Typical program and erase times assume the following conditions: 25
°C, 3.0 V V
CC, 1,000,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90
°C, V
CC = 2.7 V, 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table
12 for further information on command definitions.
6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Note: Includes all pins except V
CC. Test conditions: VCC = 3.0 V, one pin at a time.
PACKAGE PIN CAPACITANCE
Notes:
1. Sampled, not 100% tested.
2. Test conditions T
A = 25°C, f = 1.0 MHz.
FLASH DATA RETENTION
Parameter
Typ (Note 1)
Max (Note 2)
Unit
Comments
Sector Erase Time
0.4
5
sec
Excludes 00h programming
prior to erasure (Note 4)
Chip Erase Time
56
sec
Byte Program Time
5
150
µs
Excludes system level
overhead (Note 5)
Accelerated Byte/Word Program Time
4
120
µs
Word Program Time
7
210
µs
Chip Program Time
(Note 3)
Byte Mode
42
126
sec
Word Mode
28
84
Description
Min
Max
Input voltage with respect to VSS on all pins except I/O pins
(including A9, OE#, and RESET#)
–1.0 V
12.5 V
Input voltage with respect to V
SS on all I/O pins
–1.0 V
V
CC + 1.0 V
V
CC Current
–100 mA
+100 mA
Parameter
Symbol
Parameter Description
Test Setup
Typ
Max
Unit
CIN
Input Capacitance
VIN = 0
11
14
pF
C
OUT
Output Capacitance
V
OUT = 0
12
16
pF
CIN2
Control Pin Capacitance
VIN = 0
14
16
pF
C
IN3
WP#/ACC Pin Capacitance
V
IN = 0
17
20
pF
Parameter Description
Test Conditions
Min
Unit
Minimum Pattern Data Retention Time
150
°C10
Years
125
°C20
Years


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