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AM29BL162CB-65RZF Fiches technique(PDF) 10 Page - Advanced Micro Devices

No de pièce AM29BL162CB-65RZF
Description  16 Megabit (1 M x 16-Bit) CMOS 3.0 Volt-only Burst Mode Flash Memory
Download  52 Pages
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Fabricant  AMD [Advanced Micro Devices]
Site Internet  http://www.amd.com
Logo AMD - Advanced Micro Devices

AM29BL162CB-65RZF Fiches technique(HTML) 10 Page - Advanced Micro Devices

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Am29BL162C
22142F9 January 22, 2007
D A TA
SH EET
PIN CONFIGURATION
A0–A19
=
20 addresses
DQ0–DQ15 =
16 data inputs/outputs
CE#
=
Chip Enable Input. This signal shall be
asynchronous relative to CLK for the
burst mode.
OE#
=
Output Enable Input. This signal shall
be asynchronous relative to CLK for
the burst mode.
WE#
=
Write enable. This signal shall be
asynchronous relative to CLK for the
burst mode.
VSS
=
Device ground
NC
=
No connect. Pin not connected
internally
RY/BY#
=
Ready Busy output
CLK
=
Clock Input that can be tied to the
system or microprocessor clock and
provides the fundamental timing and
internal operating frequency. CLK
latches input addresses in conjunction
with LBA# input and increments the
burst address with the BAA# input.
LBA#
=
Load Burst Address input. Indicates
that the valid address is present on the
address inputs.
LBA# Low at the rising edge of the
clock latches the address on the
address inputs into the burst mode
Flash device. Data becomes available
tPACC ns of initial access time after the
rising edge of the same clock that
latches the address.
LBA# High indicates that the address
is not valid
BAA#
=
Burst Address Advance input.
Increments the address during the
burst mode operation
BAA# Low enables the burst mode
Flash device to read from the next
word when gated with the rising edge
of the clock. Data becomes available
tBACC ns of burst access time after the
rising edge of the clock
BAA # High prevents the rising edge of
the clock from advancing the data to
the next word output. The output data
remains unchanged.
IND#
=
Highest burst counter address
reached. IND# is low at the end of a
32-word burst sequence (when word
Da + 31 is output). The output wraps
around to Da on the next CLK cycle
(with BAA# low).
RESET#
=
Hardware reset input
Note: The address, data, and control signals (RY/BY#, LBA,
BAA, IND, RESET, OE#, CE#, and WE#) are 5 V tolerant.
LOGIC SYMBOL
20
16
DQ0–DQ15
A0–A19
CE#
OE#
WE#
RESET#
CLK
RY/BY#
IND#
LBA#
BAA#


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