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AD7533JN Fiches technique(PDF) 5 Page - Intersil Corporation |
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AD7533JN Fiches technique(HTML) 5 Page - Intersil Corporation |
5 / 8 page 5 2. Monitor VOUT for a -VREF (1 - 1/2 10) reading. 3. To increase VOUT, connect a series resistor, R2, (0Ω to 250 Ω) in the I OUT1 amplifier feedback loop. 4. To decrease VOUT, connect a series resistor, R1, (0Ω to 250 Ω) between the reference voltage and the V REF terminal. Bipolar (Offset Binary) Operation The circuit configuration for operating the AD7533 in the bipolar mode is given in Figure 3. Using offset binary digital input codes and positive and negative reference voltage values, 4-Quadrant multiplication can be realized. The “Digital Input Code/Analog Output Value” table for bipolar mode is given in Table 2. A “Logic 1” input at any digital input forces the corresponding ladder switch to steer the bit current to IOUT1 bus. A “Logic 0” input forces the bit current to IOUT2 bus. For any code the IOUT1 and IOUT2 bus currents are complements of one another. The current amplifier at IOUT2 changes the polarity of IOUT2 current and the transconductance amplifier at IOUT1 output sums the two currents. This configuration doubles the output range. The difference current resulting at zero offset binary code, (MSB = “Logic 1”, all other bits = “Logic 0”), is corrected by using an external resistor, (10M Ω), from VREF to IOUT2 . Offset Adjustment 5. Adjust VREF to approximately +10V. 6. Connect all digital inputs to “Logic 1”. 7. Adjust IOUT2 amplifier offset adjust trimpot for 0V ±1mV at IOUT2 amplifier output. 8. Connect MSB (Bit 1) to “Logic 1” and all other bits to “Logic 0”. 9. Adjust IOUT1 amplifier offset adjust trimpot for 0V ±1mV at VOUT. Gain Adjustment 1. Connect all digital inputs to V+. 2. Monitor VOUT for a -VREF (1 - 2 -9) volts reading. 3. To increase VOUT, connect a series resistor (R2) of up to 250 Ω between V OUT and RFEEDBACK. 4. To decrease VOUT, connect a series resistor (R1) of up to 250 Ω between the reference voltage and the V REF terminal. IOUT2 6 RFEEDBACK 6 - + IOUT1 CR1 15 16 1 4 13 3 2 MSB LSB 14 +15V VREF DATA INPUTS AD7533 ±10V R3 5K R4 5K VOUT R2 CR2 R1 R6 10M Ω FIGURE 3. BIPOLAR OPERATION (4-QUADRANT MULTIPLICATION) - + TABLE 2. UNlPOLAR BINARY CODE - AD7533 DIGITAL INPUT MSB LSB (NOTE 2) NOMINAL ANALOG OUTPUT 1111111111 1000000001 1000000000 0 0111111111 0000000001 0000000000 NOTES: 12. VOUT as shown in Figure 3. 13. Nominal Full Scale for the circuit of Figure 3 is given by: . 14. Nominal LSB magnitude for the circuit of Figure 3 is given by: . -V REF 511 512 ---------- -V REF 1 512 ---------- +V REF 1 512 ---------- +V REF 511 512 ---------- +V REF 512 512 ---------- FSR V REF 1023 512 ------------- = LSB V REF 1 512 ---------- = AD7533 |
Numéro de pièce similaire - AD7533JN |
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Description similaire - AD7533JN |
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