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SDM-09060-B1F Fiches technique(PDF) 2 Page - SIRENZA MICRODEVICES |
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SDM-09060-B1F Fiches technique(HTML) 2 Page - SIRENZA MICRODEVICES |
2 / 5 page 303 S. Technology Court Phone: (800) SMI-MMIC http://www.sirenza.com Broomfield, CO 80021 2 EDS-104211 Rev D SDM-09060-B1F 925-960 MHz 65W Power Amp Module Pin Description Pin # Function Description 1VGS1 LDMOS FET Q1 gate bias. VGSTH 3.0 to 5.0 VDC. See Notes 2, 3 and 4 2,4,7,9 Ground Module Topside ground. 3 RF Input Module RF input. This pin is internally connected to DC ground. Do not apply DC voltages to the RF leads. Care must be taken to protect against video transients that may damage the active devices. 5VGS2 LDMOS FET Q2 gate bias. VGSTH 3.0 to 5.0 VDC. See Notes 2, 3 and 4 6VD2 LDMOS FET Q2 drain bias. See Note 1. 8 RF Output Module RF output. This pin is internally connected to DC ground. Do not apply DC voltages to the RF leads. Care must be taken to protect against video transients that may damage the active devices. 10 VD1 LDMOS FET Q1 drain bias. See Note 1. Flange Ground Baseplate provides electrical ground and a thermal transfer path for the device. Proper mounting assures optimal performance and the highest reliability. See Sirenza applications note AN-054 Detailed Installation Instructions for Power Modules. Caution: ESD Sensitive Appropriate precaution in handling, packaging and testing devices must be observed. Note 1: Internal RF decoupling is included on all bias leads. No addi- tional bypass elements are required, however some applica- tions may require energy storage on the VD leads to accommodate modulated signals. Note 2: Gate voltage must be applied to VGS leads simultaneously with or after application of drain voltage to prevent potentially destructive oscillations. Bias voltages should never be applied to a module unless it is properly terminated on both input and output. Note 3: The required VGS corresponding to a specific IDQ will vary from module to module and may differ between VGS1 and VGS2 on the same module by as much as ±0.10 volts due to the normal die-to-die variation in threshold voltage for LDMOS transistors. Note 4: The threshold voltage (VGSTH) of LDMOS transistors varies with device temperature. External temperature compensation may be required. See Sirenza application notes AN-067 LDMOS Bias Temperature Compensation. Note 5: This module was designed to have it's leads hand soldered to an adjacent PCB. The maximum soldering iron tip temperature should not exceed 700° C, and the soldering iron tip should not be in direct contact with the lead for longer than 10 seconds. Refer to app note AN054 (www.sirenza.com) for further installation instructions. Absolute Maximum Ratings Parameters Value Unit Drain Voltage (VDD)35 V RF Input Power +37 dBm Load Impedance for Continuous Operation Without Damage 5:1 VSWR Control (Gate) Voltage, VDD = 0 VDC 15 V Output Device Channel Temperature +200 ºC Operating Temperature Range -20 to +90 ºC Storage Temperature Range -40 to +100 ºC Operation of this device beyond any one of these limits may cause per- manent damage. For reliable continuous operation see typical setup val- ues specified in the table on page one. 10 9 8 7 6 5 4 3 2 1 Case Flange = Ground Q2 Q1 Simplified Device Schematic |
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Description similaire - SDM-09060-B1F |
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