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CDP1857C Fiches technique(PDF) 1 Page - Intersil Corporation |
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CDP1857C Fiches technique(HTML) 1 Page - Intersil Corporation |
1 / 5 page 62 TM CDP1857C 4-Bit Bus Buffer/Separator Features • Provides Easy Connection of I/O to CDP1800-Series Microprocessor Data Bus • Non-Inverting Fully Buffered Data Transfer Description The CDP1857C is a 4-bit CMOS non-inverting bus separator designed for use in CDP1800-series microprocessor systems. It can be controlled directly by a 1800-series microprocessor without the use of additional components. The CDP1857 is designed for use as a bus buffer or separator between the 1800-series microprocessor data bus and I/O devices. It provides a chip-select (CS) input signal which, when high (1), enables the bus-separator three-state output drivers. The direction of data flow, when enabled, is controlled by the MRD input signal. In the CDP1857, when MRD = 1, it enables the three-state bus driv- ers (DB0-DB3) and transfers data from the DATA-IN lines onto the data bus. When MRD = 0, it disables the three-state bus drivers (DB0-DB3) and enables the three-state data output drivers (DO0- DO3), thus, transferring data from the data bus to the DATA-OUT ter- minals. The CDP1857 can be used as a bidirectional bus buffer by connect- ing the corresponding DI and DO terminals (Figure 1). The MRD out- put signal from the 1800-series microprocessor has the correct polarity to control the CDP1857 when it is used as I/O bus buffer/sep- arator. Therefore, the 1800-series microprocessor MRD signal can be connected directly to the MRD input of CDP1857. See Function Table 1 for use of the CDP1857 as an I/O bus buffer/separator. The CDP1857C is supplied in 16-lead hermetic, dual-in-line ceramic packages (D suffix), and in 16-lead plastic packages (E suffix). Pinout 16 LEAD DIP TOP VIEW Ordering Information PART NUMBER TEMP. RANGE PACKAGE PKG. NO. CDP1857CE -40oC to +85oCPDIP E16.3 CDP1857CD -40oC to +85oCSBDIP D16.3 TABLE 1. CDP1857 FUNCTION FOR I/O BUS SEPARATOR OPERATION CS MRD DATA BUS OUT DB0-DB3 DATA OUT DO0-DO3 0 X High Impedance High Impedance 1 0 High Impedance Data Bus 1 1 Data In High Impedance 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 DI0 DI1 DO0 DO1 DO2 DO3 VSS DI2 VDD DB0 DB1 DB2 DB3 MRD DI3 CS March 1997 File Number 1192.2 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2001. All Rights Reserved |
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