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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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ATMEGA8535-16AC Fiches technique(PDF) 98 Page - ATMEL Corporation |
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ATMEGA8535-16AC Fiches technique(HTML) 98 Page - ATMEL Corporation |
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98 / 321 page  98 ATmega8535(L) 2502K–AVR–10/06 measuring frequency only, the clearing of the ICF1 Flag is not required (if an interrupt handler is used). Output Compare Units The 16-bit comparator continuously compares TCNT1 with the Output Compare Regis- ter (OCR1x). If TCNT equals OCR1x the comparator signals a match. A match will set the Output Compare Flag (OCF1x) at the next timer clock cycle. If enabled (OCIE1x = 1), the Output Compare Flag generates an output compare interrupt. The OCF1x Flag is automatically cleared when the interrupt is executed. Alternatively the OCF1x Flag can be cleared by software by writing a logical one to its I/O bit location. The Waveform Gen- erator uses the match signal to generate an output according to operating mode set by the Waveform Generation mode (WGM13:0) bits and Compare Output mode (COM1x1:0) bits. The TOP and BOTTOM signals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation. (See “Modes of Operation” on page 101.) A special feature of output compare unit A allows it to define the Timer/Counter TOP value (i.e., counter resolution). In addition to the counter resolution, the TOP value defines the period time for waveforms generated by the Waveform Generator. Figure 43 shows a block diagram of the output compare unit. The small “n” in the regis- ter and bit names indicates the device number (n = 1 for Timer/Counter1), and the “x” indicates output compare unit (A/B). The elements of the block diagram that are not directly a part of the output compare unit are gray shaded. Figure 43. Output Compare Unit, Block Diagram The OCR1x Register is double buffered when using any of the twelve Pulse Width Mod- ulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR1x Compare Register to either TOP or BOTTOM of the counting OCFnx (Int.Req.) = (16-bit Comparator ) OCRnx Buffer (16-bit Register) OCRnxH Buf. (8-bit) OCnx TEMP (8-bit) DATA BUS (8-bit) OCRnxL Buf. (8-bit) TCNTn (16-bit Counter) TCNTnH (8-bit) TCNTnL (8-bit) COMnx1:0 WGMn3:0 OCRnx (16-bit Register) OCRnxH (8-bit) OCRnxL (8-bit) Waveform Generator TOP BOTTOM |
Numéro de pièce similaire - ATMEGA8535-16AC |
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Description similaire - ATMEGA8535-16AC |
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